Design Hierarchy

Summary

Hierarchy	Modules	Instantiations
	42	109

Dependencies

Properly architecture your design to tend to a highly hierarchical design. Modules that instantiate too many other modules have likely too many responsibilities.

Instance	Modules	Instantiations
inst_data_link	Count: 16 FIFO_DC_DROP_BAD_FRAME data_crc_check data_crc_compute data_desencapsulation data_desencapsulation_bc data_encapsulation data_err_management data_in_bc_buf data_in_buf data_link_reset data_mac data_out_bc_buf data_out_buff data_seq_check data_seq_compute data_word_id_fsm	Count: 31 gen_data_in_buff(0).inst_data_in_buf: data_in_buf (rtl) gen_data_in_buff(1).inst_data_in_buf: data_in_buf (rtl) gen_data_in_buff(2).inst_data_in_buf: data_in_buf (rtl) gen_data_in_buff(3).inst_data_in_buf: data_in_buf (rtl) gen_data_in_buff(4).inst_data_in_buf: data_in_buf (rtl) gen_data_in_buff(5).inst_data_in_buf: data_in_buf (rtl) gen_data_in_buff(6).inst_data_in_buf: data_in_buf (rtl) gen_data_in_buff(7).inst_data_in_buf: data_in_buf (rtl) gen_data_out_buff(0).inst_data_out_buff: data_out_buff (rtl) gen_data_out_buff(1).inst_data_out_buff: data_out_buff (rtl) gen_data_out_buff(2).inst_data_out_buff: data_out_buff (rtl) gen_data_out_buff(3).inst_data_out_buff: data_out_buff (rtl) gen_data_out_buff(4).inst_data_out_buff: data_out_buff (rtl) gen_data_out_buff(5).inst_data_out_buff: data_out_buff (rtl) gen_data_out_buff(6).inst_data_out_buff: data_out_buff (rtl) gen_data_out_buff(7).inst_data_out_buff: data_out_buff (rtl) inst_data_crc_check: data_crc_check (rtl) inst_data_crc_compute: data_crc_compute (rtl) inst_data_desencapsulation: data_desencapsulation (rtl) inst_data_desencapsulation_bc: data_desencapsulation_bc (rtl) inst_data_encapsulation: data_encapsulation (rtl) inst_data_err_management: data_err_management (Behavioral) inst_data_in_bc_buf: data_in_bc_buf (rtl) inst_data_link_reset: data_link_reset (rtl) inst_data_mac: data_mac (rtl) inst_data_out_bc_buf: data_out_bc_buf (rtl) inst_data_seq_check: data_seq_check (rtl) inst_data_seq_compute: data_seq_compute (rtl) inst_data_word_id_fsm: data_word_id_fsm (rtl) inst_mid_buf: FIFO_DC_DROP_BAD_FRAME (RTL) inst_mid_buf_bc: FIFO_DC_DROP_BAD_FRAME (RTL)
gen_inst_phy_plus_lane.inst_phy_plus_lane	Count: 13 SpaceFibre_64b FIFO_DC ppl_64_bus_concat_tx ppl_64_bus_split_rx ppl_64_init_hssl ppl_64_lane_ctrl_word_detect ppl_64_lane_ctrl_word_insert ppl_64_lane_init_fsm ppl_64_parallel_loopback ppl_64_rx_sync_fsm ppl_64_rx_wr_en_fifo ppl_64_skip_insertion ppl_64_word_alignment	Count: 16 inst_SpaceFibre_64b: SpaceFibre_64b (rtl) inst_fifo_in_ctrl: FIFO_DC (RTL) inst_fifo_rx_ctrl: FIFO_DC (RTL) inst_fifo_rx_data: FIFO_DC (RTL) inst_fifo_tx_data: FIFO_DC (RTL) inst_lane_ctrl_word_detect: ppl_64_lane_ctrl_word_detect (rtl) inst_lane_init_fsm: ppl_64_lane_init_fsm (rtl) inst_ppl_64_bus_concat_tx: ppl_64_bus_concat_tx (rtl) inst_ppl_64_bus_split_rx: ppl_64_bus_split_rx (rtl) inst_ppl_64_init_hssl: ppl_64_init_hssl (rtl) inst_ppl_64_lane_ctrl_word_insert: ppl_64_lane_ctrl_word_insert (rtl) inst_ppl_64_parallel_loopback: ppl_64_parallel_loopback (rtl) inst_ppl_64_rx_sync_fsm: ppl_64_rx_sync_fsm (rtl) inst_ppl_64_rx_wr_en_fifo: ppl_64_rx_wr_en_fifo (rtl) inst_ppl_64_skip_insertion: ppl_64_skip_insertion (rtl) inst_ppl_64_word_alignment: ppl_64_word_alignment (rtl)
spacefibre_light_top (top)	Count: 7 demux_rx mux_tx reset_gen data_link mib_data_link mib_phy_plus_lane phy_plus_lane_64b	Count: 7 gen_inst_phy_plus_lane.inst_phy_plus_lane: phy_plus_lane_64b (rtl) inst_data_link: data_link (Behavioral) inst_demux_rx: demux_rx (rtl) inst_mib_data_link: mib_data_link (rtl) inst_mib_phy_plus_lane: mib_phy_plus_lane (rtl) inst_mux_tx: mux_tx (rtl) inst_reset_sync_clk_from_GTY: reset_gen (rtl)
ints_fifo_dc_axis_m	Count: 2 FIFO_DC AXIS_MASTER	Count: 2 AXIS_MASTER_inst: AXIS_MASTER (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_m	Count: 2 FIFO_DC AXIS_MASTER	Count: 2 AXIS_MASTER_inst: AXIS_MASTER (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_m	Count: 2 FIFO_DC AXIS_MASTER	Count: 2 AXIS_MASTER_inst: AXIS_MASTER (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_m	Count: 2 FIFO_DC AXIS_MASTER	Count: 2 AXIS_MASTER_inst: AXIS_MASTER (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_m	Count: 2 FIFO_DC AXIS_MASTER	Count: 2 AXIS_MASTER_inst: AXIS_MASTER (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_m	Count: 2 FIFO_DC AXIS_MASTER	Count: 2 AXIS_MASTER_inst: AXIS_MASTER (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_m	Count: 2 FIFO_DC AXIS_MASTER	Count: 2 AXIS_MASTER_inst: AXIS_MASTER (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_m	Count: 2 FIFO_DC AXIS_MASTER	Count: 2 AXIS_MASTER_inst: AXIS_MASTER (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_m	Count: 2 FIFO_DC AXIS_MASTER	Count: 2 AXIS_MASTER_inst: AXIS_MASTER (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_s	Count: 2 FIFO_DC AXIS_SLAVE	Count: 2 AXIS_SLAVE_inst: AXIS_SLAVE (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_s	Count: 2 FIFO_DC AXIS_SLAVE	Count: 2 AXIS_SLAVE_inst: AXIS_SLAVE (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_s	Count: 2 FIFO_DC AXIS_SLAVE	Count: 2 AXIS_SLAVE_inst: AXIS_SLAVE (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_s	Count: 2 FIFO_DC AXIS_SLAVE	Count: 2 AXIS_SLAVE_inst: AXIS_SLAVE (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_s	Count: 2 FIFO_DC AXIS_SLAVE	Count: 2 AXIS_SLAVE_inst: AXIS_SLAVE (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_s	Count: 2 FIFO_DC AXIS_SLAVE	Count: 2 AXIS_SLAVE_inst: AXIS_SLAVE (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_s	Count: 2 FIFO_DC AXIS_SLAVE	Count: 2 AXIS_SLAVE_inst: AXIS_SLAVE (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_s	Count: 2 FIFO_DC AXIS_SLAVE	Count: 2 AXIS_SLAVE_inst: AXIS_SLAVE (implementation) fifo_dc_inst: FIFO_DC (RTL)
ints_fifo_dc_axis_s	Count: 2 FIFO_DC AXIS_SLAVE	Count: 2 AXIS_SLAVE_inst: AXIS_SLAVE (implementation) fifo_dc_inst: FIFO_DC (RTL)
gen_data_in_buff(0).inst_data_in_buf	Count: 1 FIFO_DC_AXIS_M	Count: 1 ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
gen_data_in_buff(1).inst_data_in_buf	Count: 1 FIFO_DC_AXIS_M	Count: 1 ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
gen_data_in_buff(2).inst_data_in_buf	Count: 1 FIFO_DC_AXIS_M	Count: 1 ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
gen_data_in_buff(3).inst_data_in_buf	Count: 1 FIFO_DC_AXIS_M	Count: 1 ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
gen_data_in_buff(4).inst_data_in_buf	Count: 1 FIFO_DC_AXIS_M	Count: 1 ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
gen_data_in_buff(5).inst_data_in_buf	Count: 1 FIFO_DC_AXIS_M	Count: 1 ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
gen_data_in_buff(6).inst_data_in_buf	Count: 1 FIFO_DC_AXIS_M	Count: 1 ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
gen_data_in_buff(7).inst_data_in_buf	Count: 1 FIFO_DC_AXIS_M	Count: 1 ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
gen_data_out_buff(0).inst_data_out_buff	Count: 1 FIFO_DC_AXIS_S	Count: 1 ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
gen_data_out_buff(1).inst_data_out_buff	Count: 1 FIFO_DC_AXIS_S	Count: 1 ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
gen_data_out_buff(2).inst_data_out_buff	Count: 1 FIFO_DC_AXIS_S	Count: 1 ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
gen_data_out_buff(3).inst_data_out_buff	Count: 1 FIFO_DC_AXIS_S	Count: 1 ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
gen_data_out_buff(4).inst_data_out_buff	Count: 1 FIFO_DC_AXIS_S	Count: 1 ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
gen_data_out_buff(5).inst_data_out_buff	Count: 1 FIFO_DC_AXIS_S	Count: 1 ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
gen_data_out_buff(6).inst_data_out_buff	Count: 1 FIFO_DC_AXIS_S	Count: 1 ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
gen_data_out_buff(7).inst_data_out_buff	Count: 1 FIFO_DC_AXIS_S	Count: 1 ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
inst_data_in_bc_buf	Count: 1 FIFO_DC_AXIS_M	Count: 1 ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
inst_data_out_bc_buf	Count: 1 FIFO_DC_AXIS_S	Count: 1 ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
AXIS_MASTER_inst
AXIS_MASTER_inst
AXIS_MASTER_inst
AXIS_MASTER_inst
AXIS_MASTER_inst
AXIS_MASTER_inst
AXIS_MASTER_inst
AXIS_MASTER_inst
AXIS_MASTER_inst
AXIS_SLAVE_inst
AXIS_SLAVE_inst
AXIS_SLAVE_inst
AXIS_SLAVE_inst
AXIS_SLAVE_inst
AXIS_SLAVE_inst
AXIS_SLAVE_inst
AXIS_SLAVE_inst
AXIS_SLAVE_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
fifo_dc_inst
inst_SpaceFibre_64b
inst_data_crc_check
inst_data_crc_compute
inst_data_desencapsulation
inst_data_desencapsulation_bc
inst_data_encapsulation
inst_data_err_management
inst_data_link_reset
inst_data_mac
inst_data_seq_check
inst_data_seq_compute
inst_data_word_id_fsm
inst_demux_rx
inst_fifo_in_ctrl
inst_fifo_rx_ctrl
inst_fifo_rx_data
inst_fifo_tx_data
inst_lane_ctrl_word_detect
inst_lane_init_fsm
inst_mib_data_link
inst_mib_phy_plus_lane
inst_mid_buf
inst_mid_buf_bc
inst_mux_tx
inst_ppl_64_bus_concat_tx
inst_ppl_64_bus_split_rx
inst_ppl_64_init_hssl
inst_ppl_64_lane_ctrl_word_insert
inst_ppl_64_parallel_loopback
inst_ppl_64_rx_sync_fsm
inst_ppl_64_rx_wr_en_fifo
inst_ppl_64_skip_insertion
inst_ppl_64_word_alignment
inst_reset_sync_clk_from_GTY

Note that instantiations from blackboxes or third-party IPs are not listed in this report.

VHDL Entities

Count: 71

Name	Location	Description	Details
AXIS_MASTER	AXIS_MASTER.vhd#19
AXIS_SLAVE	AXIS_SLAVE.vhd#19
FIFO_DC	fifo_dc.vhd#36
FIFO_DC_AXIS_M	FIFO_DC_AXIS_M.vhd#36
FIFO_DC_AXIS_S	FIFO_DC_AXIS_S.vhd#36
FIFO_DC_DROP_BAD_FRAME	fifo_dc_drop_bad_frame.vhd#36
SpaceFibre_64b	hssl_SpaceFibre_64b.vhd#85
data_crc_check	data_crc_check.vhd#32
data_crc_check_tb	data_crc_check_tb.vhd#22
data_crc_compute	data_crc_compute.vhd#32
data_desencapsulation	data_desencapsulation.vhd#32
data_desencapsulation_bc	data_desencapsulation_bc.vhd#32
data_encapsulation	data_encapsulation.vhd#32
data_err_management	data_err_management.vhd#32
data_in_bc_buf	data_in_bc_buf.vhd#32
data_in_buf	data_in_buf.vhd#33
data_link	data_link.vhd#31
data_link_reset	data_link_reset.vhd#32
data_mac	data_mac.vhd#32
data_out_bc_buf	data_out_bc_buf.vhd#32
data_out_buff	data_out_buf.vhd#33
data_seq_check	data_seq_check.vhd#32
data_seq_compute	data_seq_compute.vhd#32
data_word_id_fsm	data_word_id_fsm.vhd#32
demux_rx	demux_rx.vhd#32
lane_ctrl_word_detect	lane_ctrl_word_detect.vhd#33
lane_ctrl_word_insert	lane_ctrl_word_insert.vhd#33
lane_init_fsm	lane_init_fsm.vhd#32
mib_data_link	mib_data_link.vhd#29
mib_phy_plus_lane	mib_phy_plus_lane.vhd#32
mux_tx	mux_tx.vhd#32
parallel_loopback	parallel_loopback.vhd#32
phy_plus_lane	phy_plus_lane.vhd#41
phy_plus_lane_64b	phy_plus_lane_64b.vhd#35
ppl_64_bus_concat_tx	ppl_64_bus_concat_tx.vhd#32
ppl_64_bus_split_rx	ppl_64_bus_split_rx.vhd#33
ppl_64_init_hssl	ppl_64_init_hssl.vhd#32
ppl_64_lane_ctrl_word_detect	ppl_64_lane_ctrl_word_detect.vhd#32
ppl_64_lane_ctrl_word_insert	ppl_64_lane_ctrl_word_insert.vhd#32
ppl_64_lane_init_fsm	ppl_64_lane_init_fsm.vhd#32
ppl_64_parallel_loopback	ppl_64_parallel_loopback.vhd#32
ppl_64_rx_sync_fsm	ppl_64_rx_sync_fsm.vhd#30
ppl_64_rx_wr_en_fifo	ppl_64_rx_wr_en_fifo.vhd#32
ppl_64_skip_insertion	ppl_64_skip_insertion.vhd#30
ppl_64_word_alignment	ppl_64_word_alignment.vhd#33
reset_gen	reset_gen.vhd#30
rx_sync_fsm	rx_sync_fsm.vhd#32
skip_insertion	skip_insertion.vhd#33
spacefibre_light_top	spacefibre_light_top.vhd#44
spacefibre_light_top_ip	spacefibre_light_top_ip.vhd#36
subpart_tb	subpart_tb.vhd#22
tb_data_desencapsulation	tb_data_desencapsulation.vhd#22
tb_data_in_buf	data_in_buf_tb.vhd#19
tb_data_mac	data_mac_tb.vhd#22
tb_data_out_buff	data_out_buf_tb.vhd#22
tb_fifo_dc	tb_fifo_dc.vhd#7
tb_fifo_dc_axis_to_custom	tb_fifo_dc_axis_to_custom.vhd#34
tb_fifo_dc_custom_to_axis	tb_fifo_dc_custom_to_axis.vhd#16
tb_fifo_dc_drop_bad_frame	tb_fifo_dc_drop_bad_frame.vhd#7
tb_lane_ctrl_word_insert	tb_lane_ctrl_word_insert.vhd#7
tb_lane_init_fsm	tb_lane_init_fsm.vhd#7
tb_phy_hssl	tb_phy_hssl.vhd#36
tb_ppl_64_bus_split_rx	tb_ppl_64_split_rx.vhd#34
tb_ppl_64_init_hssl	tb_ppl_64_init_hssl.vhd#38
tb_ppl_64_lane_ctrl_word_detect	tb_ppl_64_lane_control_detect.vhd#34
tb_ppl_64_lane_ctrl_word_insert	tb_ppl_64_lane_ctrl_insert.vhd#34
tb_ppl_64_rx_sync_fsm	tb_ppl_64_rx_sync_fsm.vhd#34
tb_ppl_64_skip_insertion	tb_ppl_64_skip_insertion.vhd#37
tb_ppl_64_word_alignment	tb_ppl_64_word_alignment.vhd#14
tb_receive_error	tb_receive_error.vhd#21
tb_rx_sync_fsm	tb_rx_sync_fsm.vhd#7

VHDL Packages

Count: 5

Name	Location	Description	Details
PKG_TOOLS	pkg_tools.vhd#47
data_link_lib	pkg_data_link.vhd#32
pkg_phy_plus_lane	pkg_phy_plus_lane.vhd#34
pkg_phy_plus_lane_64b	pkg_phy_plus_lane_64b.vhd#34
pkg_simu	pkg_simu.vhd#38