Back to Design Hierarchy Report


Entity - lane_ctrl_word_detect

Summary

Name

Location

Description

lane_ctrl_word_detect

lane_ctrl_word_detect.vhd#33

Instantiations

Count: 1

Name

Location

Description

Details

inst_lane_ctrl_word_detect

phy_plus_lane.vhd#886

View Instantiation Details

Generics

Count: 0

Ports

Count: 23

Name

Mode

Type

Description

RST_N

in

std_logic

global reset

CLK

in

std_logic

Clock generated by GTY IP

NO_SIGNAL

out

std_logic

Flag no signal are received

RX_NEW_WORD

out

std_logic

Flag new word has been received

DETECTED_INIT1

out

std_logic

Flag INIT1 control word rxed

DETECTED_INIT2

out

std_logic

Flag INIT2 control word rxed

DETECTED_INIT3

out

std_logic

Flag INIT3 control word rxed

DETECTED_INV_INIT1

out

std_logic

Flag INV_INIT1 control word rxed

DETECTED_INV_INIT2

out

std_logic

Flag INV_INIT2 control word rxed

DETECTED_RXERR_WORD

out

std_logic

Flag RXERR detected

DETECTED_LOSS_SIGNAL

out

std_logic

Flag LOSS_SIGNAL detected

DETECTED_STANDBY

out

std_logic

Flag STANDBY detected

COMMA_K287_RXED

out

std_logic

Flag Comma K28.7 has been received

CAPABILITY

out

std_logic_vector ( 07 downto 00 )

Capability from INIT3 control word (31 downto 24)

SEND_RXERR

in

std_logic

Flag send RXERR control word to Data-Link layer when FSM leave ACTIVE_ST

NO_SIGNAL_DETECTION_ENABLED

in

std_logic

Flag to enable the no signal function

ENABLE_TRANSM_DATA

in

std_logic

Flag to enable the transmision of data

DATA_RX_FROM_RSF

in

std_logic_vector ( 31 downto 00 )

32-bit data from rx_sync_fsm

VALID_K_CARAC_FROM_RSF

in

std_logic_vector ( 03 downto 00 )

4-bit valid K character flags from rx_sync_fsm

DATA_RDY_FROM_RSF

in

std_logic

Data valid flag from rx_sync_fsm

DATA_RX_TO_DL

out

std_logic_vector ( 31 downto 00 )

32-bit data to Data-link layer

VALID_K_CARAC_TO_DL

out

std_logic_vector ( 03 downto 00 )

4-bit valid K character flags to Data-link layer

DATA_RDY_TO_DL

out

std_logic

Data valid flag to Data-link layer


Back to Design Hierarchy Report