Finite State Machines (FSM)

Count: 17

Graph

Name

Location

Reset State

States

Unreachable States

Deadlock States

Livelock States

Input Signals

Output Signals

Details

current_state

ppl_64_word_alignment.vhd#70

INIT_ST

Count: 3
ALIGNED_ST
INIT_ST
WAITING_COMMA_ST

Count: 0

Count:  0

Count: 0

4

10

Details

state

ppl_64_skip_insertion.vhd#67

TX_INIT_ST

Count: 5
TX_DATA_1_ST
TX_DATA_2_ST
TX_INIT_ST
TX_SKIP_1_ST
TX_SKIP_2_ST

Count: 0

Count:  0

Count: 0

2

8

Details

current_state

ppl_64_rx_sync_fsm.vhd#66

LOST_SYNC_ST

Count: 3
CHECK_SYNC_ST
LOST_SYNC_ST
READY_ST

Count: 0

Count:  0

Count: 0

7

10

Details

current_state

ppl_64_lane_init_fsm.vhd#99

CLEAR_LINE_ST

Count: 10
ACTIVE_ST
CLEAR_LINE_ST
CONNECTED_ST
CONNECTING_ST
DISABLED_ST
INVERT_RX_POLARITY_ST
LOSS_OF_SIGNAL_ST
PREPARE_STANDBY_ST
STARTED_ST
WAIT_ST

Count: 0

Count:  0

Count: 0

22

39

Details

init3_rxed_cnt

ppl_64_lane_init_fsm.vhd#160

2’00

Count: 2
2’00
2’01

Count: 0

Count:  0

Count: 0

5

2

Details

current_state_pll_pma

ppl_64_init_hssl.vhd#85

PMA_PLL_POWER_UP_ST

Count: 4
PMA_PLL_LOCK_ST
PMA_PLL_POWER_UP_ST
PMA_PLL_RST_PULSE_ST
TX_POWER_UP_ST

Count: 0

Count:  1
PMA_PLL_LOCK_ST

Count: 0

0

4

Details

current_state_rx_pll_pma

ppl_64_init_hssl.vhd#86

IDLE_ST

Count: 6
IDLE_ST
RX_PMA_LOCK_ST
RX_PMA_PLL_PULSE_ST
RX_PMA_POWER_UP_ST
RX_RST_PULSE_ST
RX_STARTED_ST

Count: 0

Count:  1
RX_STARTED_ST

Count: 0

4

3

Details

current_state_tx_pcs

ppl_64_init_hssl.vhd#87

IDLE_ST

Count: 3
IDLE_ST
TX_PULSE_ST
TX_STARTED_ST

Count: 0

Count:  1
TX_STARTED_ST

Count: 0

2

1

Details

current_state

ppl_64_bus_split_rx.vhd#70

IDLE_ST

Count: 5
EMPTY_BUFFER
FULL_BUFFER
FULL_FULL_BUFFER
HALF_FULL_BUFFER
IDLE_ST

Count: 0

Count:  0

Count: 0

4

7

Details

current_state

data_word_id_fsm.vhd#84

RX_NOTHING_ST

Count: 5
RX_BROADCAST_AND_DATA_FRAME_ST
RX_BROADCAST_FRAME_ST
RX_DATA_FRAME_ST
RX_IDLE_FRAME_ST
RX_NOTHING_ST

Count: 0

Count:  0

Count: 2
RX_BROADCAST_AND_DATA_FRAME_ST
RX_DATA_FRAME_ST

14

23

Details

current_state

data_out_buf.vhd#121

INIT_ST

Count: 5
ADD_EEP_ST
IDLE_ST
INIT_ST
WAIT_EIP_ST
WAIT_END_FLUSH_ST

Count: 0

Count:  0

Count: 0

9

5

Details

current_state_req

data_mac.vhd#96

IDLE_ST

Count: 5
END_ST
IDLE_ST
REQ_ST
START_ENCAPS_ST
TRANSFER_ST

Count: 3
END_ST
REQ_ST
START_ENCAPS_ST

Count:  0

Count: 0

13

1

Details

current_state

data_link_reset.vhd#69

CONF_RST_ST

Count: 4
CHECK_FAR_END_RST_ST
CONF_RST_ST
LINK_INIT_ST
NEAR_END_RST_ST

Count: 0

Count:  0

Count: 0

8

7

Details

current_state

data_in_buf.vhd#117

INIT_ST

Count: 4
ADD_EEP_ST
IDLE_ST
INIT_ST
LINK_RESET_ST

Count: 0

Count:  0

Count: 0

4

3

Details

mst_exec_state

AXIS_MASTER.vhd#57

IDLE

Count: 3
IDLE
SEND_STREAM
WAIT_READY

Count: 0

Count:  0

Count: 0

7

10

Details

state

data_err_management.vhd#71

VALID_POSITIVE_ST

Count: 4
ERROR_NEGATIVE_ST
ERROR_POSITIVE_ST
VALID_NEGATIVE_ST
VALID_POSITIVE_ST

Count: 0

Count:  0

Count: 0

5

4

Details

current_state

data_encapsulation.vhd#77

START_FRAME_ST

Count: 3
END_FRAME_ST
START_FRAME_ST
TRANSFER_ST

Count: 0

Count:  0

Count: 0

6

8

Details