Finite State Machines (FSM)
Count: 17
Graph |
Name |
Location |
Reset State |
States |
Unreachable States |
Deadlock States |
Livelock States |
Input Signals |
Output Signals |
Details |
|---|---|---|---|---|---|---|---|---|---|---|
current_state |
INIT_ST |
Count: 3 |
Count: 0 |
Count: 0 |
Count: 0 |
4 |
10 |
|||
state |
TX_INIT_ST |
Count: 5 |
Count: 0 |
Count: 0 |
Count: 0 |
2 |
8 |
|||
current_state |
LOST_SYNC_ST |
Count: 3 |
Count: 0 |
Count: 0 |
Count: 0 |
7 |
10 |
|||
current_state |
CLEAR_LINE_ST |
Count: 10 |
Count: 0 |
Count: 0 |
Count: 0 |
22 |
39 |
|||
init3_rxed_cnt |
2’00 |
Count: 2 |
Count: 0 |
Count: 0 |
Count: 0 |
5 |
2 |
|||
current_state_pll_pma |
PMA_PLL_POWER_UP_ST |
Count: 4 |
Count: 0 |
Count: 1 |
Count: 0 |
0 |
4 |
|||
current_state_rx_pll_pma |
IDLE_ST |
Count: 6 |
Count: 0 |
Count: 1 |
Count: 0 |
4 |
3 |
|||
current_state_tx_pcs |
IDLE_ST |
Count: 3 |
Count: 0 |
Count: 1 |
Count: 0 |
2 |
1 |
|||
current_state |
IDLE_ST |
Count: 5 |
Count: 0 |
Count: 0 |
Count: 0 |
4 |
7 |
|||
current_state |
RX_NOTHING_ST |
Count: 5 |
Count: 0 |
Count: 0 |
Count: 2 |
14 |
23 |
|||
current_state |
INIT_ST |
Count: 5 |
Count: 0 |
Count: 0 |
Count: 0 |
9 |
5 |
|||
current_state_req |
IDLE_ST |
Count: 5 |
Count: 3 |
Count: 0 |
Count: 0 |
13 |
1 |
|||
current_state |
CONF_RST_ST |
Count: 4 |
Count: 0 |
Count: 0 |
Count: 0 |
8 |
7 |
|||
current_state |
INIT_ST |
Count: 4 |
Count: 0 |
Count: 0 |
Count: 0 |
4 |
3 |
|||
mst_exec_state |
IDLE |
Count: 3 |
Count: 0 |
Count: 0 |
Count: 0 |
7 |
10 |
|||
state |
VALID_POSITIVE_ST |
Count: 4 |
Count: 0 |
Count: 0 |
Count: 0 |
5 |
4 |
|||
current_state |
START_FRAME_ST |
Count: 3 |
Count: 0 |
Count: 0 |
Count: 0 |
6 |
8 |