# Finite State Machines (FSM) Count: **10** |ID|Name|Location|Graph|Reset State|States|Input Signals|Output Signals|Details| |---|---|---|:---:|---|---|---:|---:|:---:| |1|mst_exec_state|AXIS_MASTER.vhd#57|Open FSM Diagram|IDLE| Count: 3
IDLE
SEND_STREAM
WAIT_READY|7|10|[View FSM Details](fsms/fsm_1.md)| |2|current_state|data_encapsulation.vhd#77|Open FSM Diagram|START_FRAME_ST| Count: 3
END_FRAME_ST
START_FRAME_ST
TRANSFER_ST|6|8|[View FSM Details](fsms/fsm_2.md)| |3|state|data_err_management.vhd#71|Open FSM Diagram|VALID_POSITIVE_ST| Count: 4
ERROR_NEGATIVE_ST
ERROR_POSITIVE_ST
VALID_NEGATIVE_ST
VALID_POSITIVE_ST|5|4|[View FSM Details](fsms/fsm_3.md)| |4|current_state|data_in_buf.vhd#117|Open FSM Diagram|INIT_ST| Count: 4
ADD_EEP_ST
IDLE_ST
INIT_ST
LINK_RESET_ST|4|3|[View FSM Details](fsms/fsm_4.md)| |5|current_state|data_link_reset.vhd#69|Open FSM Diagram|CONF_RST_ST| Count: 4
CHECK_FAR_END_RST_ST
CONF_RST_ST
LINK_INIT_ST
NEAR_END_RST_ST|8|7|[View FSM Details](fsms/fsm_5.md)| |6|current_state_req|data_mac.vhd#96|Open FSM Diagram|IDLE_ST| Count: 2
END_ST
IDLE_ST
REQ_ST
START_ENCAPS_ST
TRANSFER_ST|13|1|[View FSM Details](fsms/fsm_6.md)| |7|current_state|data_out_buf.vhd#121|Open FSM Diagram|INIT_ST| Count: 5
ADD_EEP_ST
IDLE_ST
INIT_ST
WAIT_EIP_ST
WAIT_END_FLUSH_ST|9|5|[View FSM Details](fsms/fsm_7.md)| |8|current_state|data_word_id_fsm.vhd#84|Open FSM Diagram|RX_NOTHING_ST| Count: 5
RX_BROADCAST_AND_DATA_FRAME_ST
RX_BROADCAST_FRAME_ST
RX_DATA_FRAME_ST
RX_IDLE_FRAME_ST
RX_NOTHING_ST|13|23|[View FSM Details](fsms/fsm_8.md)| |9|current_state|lane_init_fsm.vhd#98|Open FSM Diagram|CLEAR_LINE_ST| Count: 10
ACTIVE_ST
CLEAR_LINE_ST
CONNECTED_ST
CONNECTING_ST
DISABLED_ST
INVERT_RX_POLARITY_ST
LOSS_OF_SIGNAL_ST
PREPARE_STANDBY_ST
STARTED_ST
WAIT_ST|20|39|[View FSM Details](fsms/fsm_9.md)| |10|current_state|rx_sync_fsm.vhd#67|Open FSM Diagram|LOST_SYNC_ST| Count: 3
CHECK_SYNC_ST
LOST_SYNC_ST
READY_ST|10|11|[View FSM Details](fsms/fsm_10.md)|