Clock Domains

Clock Management Module (CMM)

phy_plus_lane instantiated as inst_phy_plus_lane

All clocks should be generated within a unique clock management module (CMM). A dedicated CMM brings a lot in terms of reuse and portability. Because all vendor-specific clock elements are generated within the same module, it is easier to replace this module to target other FPGAs.

Clock Domains

Count: 4

Name: Origin	Graph	Rising	Falling	Details
CLK   - CLK: spacefibre_light_top.vhd#45 (Port)		✔	✗
inst_phy_plus_lane.clk_tx   - O: phy_plus_lane.vhd#991 (Blackbox port: O)		✔	✗
AXIS_ACLK_TX_DL   - AXIS_ACLK_TX_DL: spacefibre_light_top.vhd#58 (Port)		✔	✗
AXIS_ACLK_RX_DL   - AXIS_ACLK_RX_DL: spacefibre_light_top.vhd#65 (Port)		✔	✗

A clock domain used for both rising and falling edges is counted as two separate clock domains.