Clock Domains

Clock Management Module (CMM)

None identified.

All clocks should be generated within a unique clock management module (CMM). A dedicated CMM brings a lot in terms of reuse and portability. Because all vendor-specific clock elements are generated within the same module, it is easier to replace this module to target other FPGAs.

Clock Domains

Count	Graph
5

Name: Origin	Rising	Falling	Details
CLK   - CLK: spacefibre_light_top.vhd#51 (Port)	✔	✗
gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx   - hssl_clock_o: hssl_SpaceFibre_64b.vhd#156 (Blackbox port: hssl_clock_o)	✔	✗
AXIS_ACLK_RX_DL   - AXIS_ACLK_RX_DL: spacefibre_light_top.vhd#72 (Port)	✔	✗
AXIS_ACLK_TX_DL   - AXIS_ACLK_TX_DL: spacefibre_light_top.vhd#65 (Port)	✔	✗
inst_reset_sync_clk_from_GTY.reset_gen_rr_n   - inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)	✔	✗

A clock domain used for both rising and falling edges is counted as two separate clock domains.