Clock Domain Details

Summary

Name: Origin	Graph	Rising	Falling	Number of flip-flops using this clock domain	Number of instances using this clock domain
inst_phy_plus_lane.clk_tx - O: phy_plus_lane.vhd#991 (Blackbox port: O)		✔	✗	129/1245 (10.36%)	11/103

Instances using this clock domain

Count: 11

Instance	Rising	Falling
TOP (spacefibre_light_top) > inst_reset_sync_clk_from_GTY (reset_gen)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_lane_init_fsm (lane_init_fsm)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_in_ctrl (FIFO_DC)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_lane_ctrl_word_insert (lane_ctrl_word_insert)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_skip_insertion (skip_insertion)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_parallel_loopback (parallel_loopback)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_rx_sync_fsm (rx_sync_fsm)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_lane_ctrl_word_detect (lane_ctrl_word_detect)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_rx_data (FIFO_DC)	✔	✗
TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_out_ctrl (FIFO_DC)	✔	✗

Flip-flops using this clock domain

Count: 129

Rising-edge usage

Count: 129
fifo_dc.vhd#199
fifo_dc.vhd#222
fifo_dc.vhd#240
fifo_dc.vhd#256
fifo_dc.vhd#300
fifo_dc.vhd#321
fifo_dc.vhd#344
fifo_dc.vhd#362
fifo_dc.vhd#378
fifo_dc.vhd#440
reset_gen.vhd#56
lane_ctrl_word_detect.vhd#80
lane_ctrl_word_insert.vhd#79
lane_init_fsm.vhd#183
lane_init_fsm.vhd#283
lane_init_fsm.vhd#422
lane_init_fsm.vhd#442
lane_init_fsm.vhd#482
lane_init_fsm.vhd#505
lane_init_fsm.vhd#538
lane_init_fsm.vhd#571
lane_init_fsm.vhd#611
lane_init_fsm.vhd#661
lane_init_fsm.vhd#694
lane_init_fsm.vhd#731
parallel_loopback.vhd#64
rx_sync_fsm.vhd#135
rx_sync_fsm.vhd#86
skip_insertion.vhd#63

Falling-edge usage

Count: 0

Note that there could be fewer source code locations than the number of flip-flops because several flip-flops can be inferred from the same piece of code.

Back to Clock Domains Report