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Clock Domain Details

Summary

Name: Origin	Graph	Rising	Falling	Number of flip-flops using this clock domain	Number of instances using this clock domain
gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx   - hssl_clock_o: hssl_SpaceFibre_64b.vhd#156 (Blackbox port: hssl_clock_o)		✔	✗	171/1320 (12.95%)	13/109

Instances using this clock domain

Count: 13

Instance	Rising	Falling
TOP (spacefibre_light_top) > inst_reset_sync_clk_from_GTY (reset_gen)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_rx_sync_fsm (ppl_64_rx_sync_fsm)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_lane_ctrl_word_detect (ppl_64_lane_ctrl_word_detect)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_rx_wr_en_fifo (ppl_64_rx_wr_en_fifo)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_rx_data (FIFO_DC)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_rx_ctrl (FIFO_DC)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_lane_init_fsm (ppl_64_lane_init_fsm)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_in_ctrl (FIFO_DC)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_lane_ctrl_word_insert (ppl_64_lane_ctrl_word_insert)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_skip_insertion (ppl_64_skip_insertion)	✔	✗
TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_word_alignment (ppl_64_word_alignment)	✔	✗

Flip-flops using this clock domain

Count: 171

Rising-edge usage

Count: 171
fifo_dc.vhd#199
fifo_dc.vhd#222
fifo_dc.vhd#240
fifo_dc.vhd#256
fifo_dc.vhd#300
fifo_dc.vhd#321
fifo_dc.vhd#344
fifo_dc.vhd#362
fifo_dc.vhd#378
fifo_dc.vhd#440
reset_gen.vhd#56
phy_plus_lane_64b.vhd#722
phy_plus_lane_64b.vhd#734
ppl_64_lane_ctrl_word_detect.vhd#132
ppl_64_lane_ctrl_word_detect.vhd#231
ppl_64_lane_ctrl_word_detect.vhd#330
ppl_64_lane_ctrl_word_detect.vhd#347
ppl_64_lane_ctrl_word_detect.vhd#361
ppl_64_lane_ctrl_word_insert.vhd#238
ppl_64_lane_ctrl_word_insert.vhd#86
ppl_64_lane_init_fsm.vhd#1046
ppl_64_lane_init_fsm.vhd#190
ppl_64_lane_init_fsm.vhd#295
ppl_64_lane_init_fsm.vhd#436
ppl_64_lane_init_fsm.vhd#455
ppl_64_lane_init_fsm.vhd#511
ppl_64_lane_init_fsm.vhd#534
ppl_64_lane_init_fsm.vhd#581
ppl_64_lane_init_fsm.vhd#628
ppl_64_lane_init_fsm.vhd#696
ppl_64_lane_init_fsm.vhd#731
ppl_64_lane_init_fsm.vhd#803
ppl_64_lane_init_fsm.vhd#883
ppl_64_lane_init_fsm.vhd#970
ppl_64_rx_sync_fsm.vhd#127
ppl_64_rx_sync_fsm.vhd#229
ppl_64_rx_sync_fsm.vhd#92
ppl_64_rx_wr_en_fifo.vhd#63
ppl_64_skip_insertion.vhd#83
ppl_64_word_alignment.vhd#401
ppl_64_word_alignment.vhd#86

Falling-edge usage

Count: 0

Note that there could be fewer source code locations than the number of flip-flops because several flip-flops can be inferred from the same piece of code.

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