1 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
2 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
3 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
4 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
5 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
6 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
7 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
8 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
9 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
10 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
11 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
12 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
13 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
14 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
15 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
16 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
17 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440 |
18 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#256 |
19 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#256 |
20 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
21 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
22 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
23 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
24 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
25 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
26 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
27 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
28 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
29 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
30 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
31 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
32 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
33 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
34 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
35 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
36 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
37 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
38 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
39 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
40 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
41 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#199 |
42 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
43 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
44 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
45 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
46 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#440 |
47 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
48 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
49 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
50 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
51 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
52 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
53 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
54 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
55 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
56 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
57 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
58 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
59 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
60 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
61 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
62 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
63 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
64 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
65 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
66 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
67 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
68 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
69 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
70 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
71 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
72 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
73 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
74 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
75 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
76 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
77 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
78 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
79 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
80 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
81 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
82 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
83 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
84 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
85 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
86 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
87 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
88 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
89 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
90 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
91 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
92 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
93 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
94 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
95 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
96 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
97 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
98 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
99 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
100 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
101 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
102 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
103 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440 |
104 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
105 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
106 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
107 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
108 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440 |
109 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440 |
110 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
111 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
112 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#256 |
113 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
114 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
115 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
116 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
117 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
118 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
119 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
120 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
121 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
122 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
123 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
124 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
125 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
126 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
127 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
128 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
129 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
130 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#199 |
131 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
132 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
133 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
134 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
135 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
136 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#199 |
137 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
138 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
139 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
140 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
141 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
142 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
143 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
144 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
145 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
146 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
147 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
148 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
149 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
150 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
151 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
152 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
153 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
154 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
155 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
156 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
157 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
158 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
159 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
160 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
161 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
162 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
163 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
164 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
165 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
166 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
167 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
168 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
169 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
170 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
171 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
172 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
173 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
174 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
175 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
176 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
177 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
178 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
179 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
180 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
181 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
182 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
183 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
184 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
185 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
186 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
187 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
188 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
189 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
190 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
191 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
192 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
193 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
194 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
195 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
196 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
197 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
198 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
199 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
200 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
201 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
202 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
203 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
204 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
205 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
206 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
207 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
208 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
209 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
210 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
211 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
212 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
213 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
214 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
215 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
216 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
217 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
218 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
219 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
220 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
221 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
222 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
223 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
224 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
225 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
226 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
227 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
228 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
229 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
230 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
231 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
232 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
233 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
234 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
235 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
236 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
237 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
238 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
239 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
240 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
241 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
242 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
243 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
244 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
245 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
246 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
247 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
248 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
249 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
250 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
251 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
252 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
253 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
254 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
255 |
|
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
256 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
257 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
258 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
259 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
260 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
261 |
|
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
262 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#222 |
263 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#240 |
264 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#199 |
265 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440 |
266 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440 |
267 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#222 |
268 |
|
Clock domain: inst_phy_plus_lane.clk_tx (rising)
Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_phy_plus_lane (phy_plus_lane) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#240 |