Clock Domain Details

Summary

Name: Origin	Graph	Rising	Falling	Number of flip-flops using this clock domain	Number of instances using this clock domain
AXIS_ACLK_RX_DL - AXIS_ACLK_RX_DL: spacefibre_light_top.vhd#65 (Port)		✔	✗	20/1245 (1.61%)	3/103

Instances using this clock domain

Count: 3

Instance	Rising	Falling
TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf)	✔	✗
TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > AXIS_MASTER_inst (AXIS_MASTER)	✔	✗
TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC)	✔	✗

Flip-flops using this clock domain

Count: 20

Rising-edge usage

Count: 20
fifo_dc.vhd#300
fifo_dc.vhd#321
fifo_dc.vhd#344
fifo_dc.vhd#362
fifo_dc.vhd#378
AXIS_MASTER.vhd#84
AXIS_MASTER.vhd#98
data_in_buf.vhd#194
data_in_buf.vhd#276

Falling-edge usage

Count: 0

Note that there could be fewer source code locations than the number of flip-flops because several flip-flops can be inferred from the same piece of code.

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