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FSM #13: init3_rxed_cnt

Summary

Name

Location

Graph

Reset State

States

Input Signals

Output Signals

init3_rxed_cnt

ppl_64_lane_init_fsm.vhd#160

Open FSM Diagram

00

Count: 2
00
01

5

2

Input Signals

Count: 5

Name

Declaration

CLK

ppl_64_lane_init_fsm.vhd#35

DETECTED_INIT3_PLCWD

ppl_64_lane_init_fsm.vhd#43

DETECTED_RXERR_WORD_PLCWD

ppl_64_lane_init_fsm.vhd#46

RST_N

ppl_64_lane_init_fsm.vhd#34

current_state_r

ppl_64_lane_init_fsm.vhd#100

Output Signals

Count: 2

Name

Declaration

init3_rxed_x3

ppl_64_lane_init_fsm.vhd#161

init3_rxed_x3_fw

ppl_64_lane_init_fsm.vhd#162

Transition table

From

To

Input Control Signals

00

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

00

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

00

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

00

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

00

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

00

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

00

00

CLK: ppl_64_lane_init_fsm.vhd#35
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

00

01

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

01

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

01

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

01

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

01

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

01

00

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

01

00

CLK: ppl_64_lane_init_fsm.vhd#35
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

01

01

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

01

01

CLK: ppl_64_lane_init_fsm.vhd#35
DETECTED_INIT3_PLCWD: ppl_64_lane_init_fsm.vhd#43
DETECTED_RXERR_WORD_PLCWD: ppl_64_lane_init_fsm.vhd#46
RST_N: ppl_64_lane_init_fsm.vhd#34
current_state_r: ppl_64_lane_init_fsm.vhd#100

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