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FSM #1: mst_exec_state

Summary

Name

Location

Graph

Reset State

States

Input Signals

Output Signals

mst_exec_state

AXIS_MASTER.vhd#57

Open FSM Diagram

IDLE

Count: 3
IDLE
SEND_STREAM
WAIT_READY

7

10

Input Signals

Count: 7

Name

Declaration

axis_tvalid

AXIS_MASTER.vhd#60

end_frame

AXIS_MASTER.vhd#70

m00_axis_tready

AXIS_MASTER.vhd#42

m00_axis_tvalid

AXIS_MASTER.vhd#39

rd_data_en

AXIS_MASTER.vhd#33

rd_data_vld

AXIS_MASTER.vhd#32

start_frame

AXIS_MASTER.vhd#69

Output Signals

Count: 10

Name

Declaration

axis_tlast

AXIS_MASTER.vhd#61

axis_tvalid

AXIS_MASTER.vhd#60

end_frame

AXIS_MASTER.vhd#70

m00_axis_tdata

AXIS_MASTER.vhd#40

m00_axis_tlast

AXIS_MASTER.vhd#41

m00_axis_tuser

AXIS_MASTER.vhd#43

m00_axis_tvalid

AXIS_MASTER.vhd#39

start_frame

AXIS_MASTER.vhd#69

stream_data_out

AXIS_MASTER.vhd#64

stream_user_out

AXIS_MASTER.vhd#67

Transition table

From

To

Input Control Signals

IDLE

IDLE

end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32

IDLE

IDLE

end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32

IDLE

SEND_STREAM

end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32

IDLE

WAIT_READY

end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32

IDLE

WAIT_READY

end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32

SEND_STREAM

IDLE

m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32
start_frame: AXIS_MASTER.vhd#69

SEND_STREAM

SEND_STREAM

m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32
start_frame: AXIS_MASTER.vhd#69

SEND_STREAM

WAIT_READY

m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32
start_frame: AXIS_MASTER.vhd#69

SEND_STREAM

WAIT_READY

m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32
start_frame: AXIS_MASTER.vhd#69

SEND_STREAM

WAIT_READY

m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32
start_frame: AXIS_MASTER.vhd#69

SEND_STREAM

WAIT_READY

m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
rd_data_vld: AXIS_MASTER.vhd#32
start_frame: AXIS_MASTER.vhd#69

WAIT_READY

IDLE

axis_tvalid: AXIS_MASTER.vhd#60
end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
m00_axis_tvalid: AXIS_MASTER.vhd#39
rd_data_en: AXIS_MASTER.vhd#33
start_frame: AXIS_MASTER.vhd#69

WAIT_READY

IDLE

end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
rd_data_en: AXIS_MASTER.vhd#33
start_frame: AXIS_MASTER.vhd#69

WAIT_READY

SEND_STREAM

axis_tvalid: AXIS_MASTER.vhd#60
end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
m00_axis_tvalid: AXIS_MASTER.vhd#39
rd_data_en: AXIS_MASTER.vhd#33
start_frame: AXIS_MASTER.vhd#69

WAIT_READY

SEND_STREAM

axis_tvalid: AXIS_MASTER.vhd#60
end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
m00_axis_tvalid: AXIS_MASTER.vhd#39
rd_data_en: AXIS_MASTER.vhd#33
start_frame: AXIS_MASTER.vhd#69

WAIT_READY

SEND_STREAM

axis_tvalid: AXIS_MASTER.vhd#60
end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
m00_axis_tvalid: AXIS_MASTER.vhd#39
rd_data_en: AXIS_MASTER.vhd#33
start_frame: AXIS_MASTER.vhd#69

WAIT_READY

SEND_STREAM

axis_tvalid: AXIS_MASTER.vhd#60
end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
m00_axis_tvalid: AXIS_MASTER.vhd#39
rd_data_en: AXIS_MASTER.vhd#33
start_frame: AXIS_MASTER.vhd#69

WAIT_READY

WAIT_READY

axis_tvalid: AXIS_MASTER.vhd#60
end_frame: AXIS_MASTER.vhd#70
m00_axis_tready: AXIS_MASTER.vhd#42
m00_axis_tvalid: AXIS_MASTER.vhd#39
rd_data_en: AXIS_MASTER.vhd#33
start_frame: AXIS_MASTER.vhd#69

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