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FSM #11: current_state_rx_pll_pma

Summary

Name	Location	Graph	Reset State	States	Input Signals	Output Signals
current_state_rx_pll_pma	ppl_64_init_hssl.vhd#86		IDLE_ST	Count: 6 IDLE_ST RX_PMA_LOCK_ST RX_PMA_PLL_PULSE_ST RX_PMA_POWER_UP_ST RX_RST_PULSE_ST RX_STARTED_ST	4	3

Input Signals

Count: 4

Name	Declaration
CDR_PLIF	ppl_64_init_hssl.vhd#38
RECEIVER_DISABLED_PLIF	ppl_64_init_hssl.vhd#37
RX_PMA_LL_SLOW_LOCKED_HSSL	ppl_64_init_hssl.vhd#49
pma_pll_seq_end	ppl_64_init_hssl.vhd#88

Output Signals

Count: 3

Name	Declaration
RX_PMA_PWR_UP_PLIH	ppl_64_init_hssl.vhd#47
RX_PMA_RST_N_PLIH	ppl_64_init_hssl.vhd#48
RX_RST_N_PLIH	ppl_64_init_hssl.vhd#50

Transition table

From	To	Input Control Signals
IDLE_ST	IDLE_ST	RECEIVER_DISABLED_PLIF: ppl_64_init_hssl.vhd#37 pma_pll_seq_end: ppl_64_init_hssl.vhd#88
IDLE_ST	RX_PMA_POWER_UP_ST	RECEIVER_DISABLED_PLIF: ppl_64_init_hssl.vhd#37 pma_pll_seq_end: ppl_64_init_hssl.vhd#88
RX_PMA_POWER_UP_ST	RX_PMA_POWER_UP_ST	CDR_PLIF: ppl_64_init_hssl.vhd#38
RX_PMA_POWER_UP_ST	RX_PMA_PLL_PULSE_ST	CDR_PLIF: ppl_64_init_hssl.vhd#38
RX_PMA_PLL_PULSE_ST	RX_PMA_LOCK_ST
RX_PMA_LOCK_ST	RX_PMA_LOCK_ST	RX_PMA_LL_SLOW_LOCKED_HSSL: ppl_64_init_hssl.vhd#49
RX_PMA_LOCK_ST	RX_RST_PULSE_ST	RX_PMA_LL_SLOW_LOCKED_HSSL: ppl_64_init_hssl.vhd#49
RX_RST_PULSE_ST	RX_STARTED_ST
RX_STARTED_ST	RX_STARTED_ST

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