FSM #9: current_state

Summary

Name	Location	Graph	Reset State	States	Input Signals	Output Signals
current_state	ppl_64_bus_split_rx.vhd#70		IDLE_ST	Count: 5 EMPTY_BUFFER FULL_BUFFER FULL_FULL_BUFFER HALF_FULL_BUFFER IDLE_ST	4	7

Input Signals

Count: 4

Name	Declaration
DATA_RDY_RX_PLFRD	ppl_64_bus_split_rx.vhd#50
FIFO_RX_DATA_VALID_PLFRD	ppl_64_bus_split_rx.vhd#47
FIFO_RX_EMPTY_PLFRD	ppl_64_bus_split_rx.vhd#48
FIFO_RX_RD_EN_DL	ppl_64_bus_split_rx.vhd#38

Output Signals

Count: 7

Name	Declaration
DATA_RX_PLBSR	ppl_64_bus_split_rx.vhd#39
FIFO_RX_DATA_VALID_PLBSR	ppl_64_bus_split_rx.vhd#40
FIFO_RX_RD_EN_PLBSR	ppl_64_bus_split_rx.vhd#45
VALID_K_CHARAC_RX_PLBSR	ppl_64_bus_split_rx.vhd#41
buffer_data_96	ppl_64_bus_split_rx.vhd#71
buffer_k_char_12	ppl_64_bus_split_rx.vhd#72
fifo_rx_rd_en_plbsr_i	ppl_64_bus_split_rx.vhd#73

Transition table

From	To	Input Control Signals
IDLE_ST	IDLE_ST	FIFO_RX_EMPTY_PLFRD: ppl_64_bus_split_rx.vhd#48
IDLE_ST	EMPTY_BUFFER	FIFO_RX_EMPTY_PLFRD: ppl_64_bus_split_rx.vhd#48
EMPTY_BUFFER	EMPTY_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47
EMPTY_BUFFER	EMPTY_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
EMPTY_BUFFER	EMPTY_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
EMPTY_BUFFER	HALF_FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
EMPTY_BUFFER	HALF_FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
EMPTY_BUFFER	HALF_FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
EMPTY_BUFFER	FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
HALF_FULL_BUFFER	EMPTY_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
HALF_FULL_BUFFER	HALF_FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
HALF_FULL_BUFFER	HALF_FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
HALF_FULL_BUFFER	HALF_FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
HALF_FULL_BUFFER	FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
HALF_FULL_BUFFER	FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
HALF_FULL_BUFFER	FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
HALF_FULL_BUFFER	FULL_FULL_BUFFER	DATA_RDY_RX_PLFRD: ppl_64_bus_split_rx.vhd#50 FIFO_RX_DATA_VALID_PLFRD: ppl_64_bus_split_rx.vhd#47 FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
FULL_BUFFER	HALF_FULL_BUFFER	FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
FULL_BUFFER	FULL_BUFFER	FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
FULL_FULL_BUFFER	FULL_BUFFER	FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38
FULL_FULL_BUFFER	FULL_FULL_BUFFER	FIFO_RX_RD_EN_DL: ppl_64_bus_split_rx.vhd#38

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