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Entity - AXIS_MASTER

Summary

Name	Location	Description
AXIS_MASTER	AXIS_MASTER.vhd#19

Instantiations

Count: 9

Name	Location	Description	Details
AXIS_MASTER_inst	FIFO_DC_AXIS_M.vhd#154
AXIS_MASTER_inst	FIFO_DC_AXIS_M.vhd#154
AXIS_MASTER_inst	FIFO_DC_AXIS_M.vhd#154
AXIS_MASTER_inst	FIFO_DC_AXIS_M.vhd#154
AXIS_MASTER_inst	FIFO_DC_AXIS_M.vhd#154
AXIS_MASTER_inst	FIFO_DC_AXIS_M.vhd#154
AXIS_MASTER_inst	FIFO_DC_AXIS_M.vhd#154
AXIS_MASTER_inst	FIFO_DC_AXIS_M.vhd#154
AXIS_MASTER_inst	FIFO_DC_AXIS_M.vhd#154

Generics

Count: 3

Name	Type	Default value	Description
G_DWIDTH	integer	36	Total data width
M_AXIS_TDATA_WIDTH	integer	32	TData Width
M_AXIS_TUSER_WIDTH	integer	4	TUser Width

Ports

Count: 10

Name	Mode	Type	Description
rd_data	in	std_logic_vector ( G_DWIDTH - 1 downto 0 )	Data read bus
rd_data_vld	in	std_logic	Read command
rd_data_en	out	std_logic	Data valid
m00_axis_aclk	in	std_logic	Clock input for the AXI Stream Master interface
m00_axis_aresetn	in	std_logic	Active-low reset input for the AXI Stream Master interface
m00_axis_tvalid	out	std_logic	Indicates that the data on m00_axis_tdata is valid
m00_axis_tdata	out	std_logic_vector ( M_AXIS_TDATA_WIDTH - 1 downto 0 )	Data output bus for the AXI Stream Master interface
m00_axis_tlast	out	std_logic	Indicates the last transfer in a packet
m00_axis_tready	in	std_logic	Indicates that the receiver is ready to accept data
m00_axis_tuser	out	std_logic_vector ( M_AXIS_TUSER_WIDTH - 1 downto 0 )	User-defined data output bus for the AXI Stream Master interface

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