Back to Design Hierarchy Report
Entity - rx_sync_fsm
Summary
Name |
Location |
Description |
---|---|---|
rx_sync_fsm |
Instantiations
Count: 1
Name |
Location |
Description |
Details |
---|---|---|---|
inst_rx_sync_fsm |
Generics
Count: 0
Ports
Count: 15
Name |
Mode |
Type |
Description |
---|---|---|---|
in |
std_logic |
MAIN CLOCK |
|
in |
std_logic |
global reset |
|
in |
std_logic |
Clock generated by GTY IP |
|
in |
std_logic |
Lane reset command from Data-Link Layer. |
|
out |
std_logic_vector ( 31 downto 00 ) |
32-bit data to lane_ctrl_word_detect |
|
out |
std_logic_vector ( 03 downto 00 ) |
4-bit valid K character flags to lane_ctrl_word_detect |
|
out |
std_logic |
Data valid flag to lane_ctrl_word_detect |
|
in |
std_logic_vector ( 31 downto 00 ) |
32-bit data from GTY IP |
|
in |
std_logic_vector ( 03 downto 00 ) |
4-bit valid K character flags from GTY IP |
|
in |
std_logic |
Data valid flag from GTY IP |
|
in |
std_logic_vector ( 03 downto 00 ) |
Invalid character flags from GTY IP |
|
in |
std_logic_vector ( 03 downto 00 ) |
Disparity error flags from GTY IP |
|
in |
std_logic |
RX word realign from GTY IP |
|
in |
std_logic |
Flag indicates that a comma is detected on the word receive |
|
in |
std_logic |
Asserts or de-asserts LaneReset for the lane |