Entity - data_link
Summary
Name |
Location |
Description |
|---|---|---|
data_link |
Instantiations
Count: 1
Name |
Location |
Description |
Details |
|---|---|---|---|
inst_data_link |
Generics
Count: 1
Name |
Type |
Default value |
Description |
|---|---|---|---|
integer |
8 |
Number of virtual channel |
Ports
Count: 69
Name |
Mode |
Type |
Description |
|---|---|---|---|
in |
std_logic |
global reset |
|
in |
std_logic |
Clock generated by GTY IP |
|
in |
std_logic_vector ( G_VC_NUM downto 0 ) |
Active-low asynchronous reset signals for each virtual channel (VC) in the TX path |
|
in |
std_logic_vector ( G_VC_NUM downto 0 ) |
Clock signals for each VC in the TX path |
|
out |
std_logic_vector ( G_VC_NUM downto 0 ) |
Indicates that the data link layer is ready to accept data on each VC |
|
in |
vc_data_array ( G_VC_NUM downto 0 ) |
Data signals from the network layer to the data link layer for each VC |
|
in |
vc_k_array ( G_VC_NUM downto 0 ) |
Sideband information (e.g., control or metadata) from the network layer to the data link layer for each VC |
|
in |
std_logic_vector ( G_VC_NUM downto 0 ) |
Indicates the last transfer in a packet/transaction on each VC |
|
in |
std_logic_vector ( G_VC_NUM downto 0 ) |
Indicates that valid data is available on the TX data bus for each VC |
|
in |
std_logic_vector ( G_VC_NUM downto 0 ) |
Active-low asynchronous reset signals for each VC in the RX path |
|
in |
std_logic_vector ( G_VC_NUM downto 0 ) |
Clock signals for each VC in the RX path |
|
in |
std_logic_vector ( G_VC_NUM downto 0 ) |
Indicates that the network layer is ready to receive data on each VC |
|
out |
vc_data_array ( G_VC_NUM downto 0 ) |
Data signals from the data link layer to the network layer for each VC |
|
out |
vc_k_array ( G_VC_NUM downto 0 ) |
Sideband information from the data link layer to the network layer for each VC |
|
out |
std_logic_vector ( G_VC_NUM downto 0 ) |
Indicates the last transfer in a packet/transaction on each VC |
|
out |
std_logic_vector ( G_VC_NUM downto 0 ) |
Indicates that valid data is available on the RX data bus for each VC |
|
in |
std_logic_vector ( 7 downto 0 ) |
Current time slot |
|
out |
std_logic_vector ( 31 downto 00 ) |
Data parallel to be send from Data-Link Layer |
|
out |
std_logic_vector ( 07 downto 00 ) |
Capability send on TX link in INIT3 control word |
|
out |
std_logic |
Flag to write data in FIFO TX |
|
out |
std_logic_vector ( 03 downto 00 ) |
K charachter valid in the 32-bit DATA_TX_DL vector |
|
in |
std_logic |
Flag full of the FIFO TX |
|
out |
std_logic |
Flag to read data in FIFO RX |
|
in |
std_logic_vector ( 31 downto 00 ) |
Data parallel to be received to Data-Link Layer |
|
in |
std_logic |
Flag EMPTY of the FIFO RX |
|
in |
std_logic |
Flag DATA_VALID of the FIFO RX |
|
in |
std_logic_vector ( 03 downto 00 ) |
K charachter valid in the 32-bit DATA_TR_PPL vector |
|
in |
std_logic_vector ( 07 downto 00 ) |
Capability field receive in INIT3 control word |
|
in |
std_logic |
Lane Active flag for the DATA Link Layer |
|
out |
std_logic |
Lane Reset command |
|
in |
std_logic |
Reset the link and all configuration register of the Data Link layer |
|
in |
std_logic |
Reset the link |
|
in |
std_logic |
Enable automatic link reset on NACK reception |
|
in |
std_logic |
Up for instant link reset on NACK reception, down for link reset at the end of the current received frame on NACK reception |
|
in |
std_logic_vector ( G_VC_NUM downto 0 ) |
Pause the corresponding virtual channel after the end of current transmission |
|
in |
std_logic_vector ( G_VC_NUM - 1 downto 0 ) |
Enable the corresponding virtual channel continuous mode |
|
out |
std_logic_vector ( 8 - 1 downto 0 ) |
SEQ_NUMBER in transmission |
|
out |
std_logic_vector ( 8 - 1 downto 0 ) |
SEQ_NUMBER in reception |
|
out |
std_logic_vector ( G_VC_NUM - 1 downto 0 ) |
Indicates if each corresponding far-end input buffer has credit |
|
out |
std_logic_vector ( G_VC_NUM - 1 downto 0 ) |
Indicates input buffer overflow |
|
out |
std_logic_vector ( G_VC_NUM - 1 downto 0 ) |
Indicates overflow of each corresponding input buffer |
|
out |
std_logic |
CRC long error |
|
out |
std_logic |
CRC short error |
|
out |
std_logic |
Frame error |
|
out |
std_logic |
Sequence error |
|
out |
std_logic |
Far-end link reset status |
|
out |
std_logic_vector ( G_VC_NUM downto 0 ) |
Indicates that corresponding channel finished emitting a frame |
|
out |
std_logic_vector ( G_VC_NUM downto 0 ) |
Indicates that corresponding channel is emitting a frame |
|
out |
std_logic_vector ( 6 downto 0 ) |
Indicate the number of data transmitted in last frame emitted |
|
out |
std_logic_vector ( 6 downto 0 ) |
Indicate the number of data received in last frame received |
|
out |
std_logic_vector ( 2 downto 0 ) |
ACK counter TX |
|
out |
std_logic_vector ( 2 downto 0 ) |
NACK counter TX |
|
out |
std_logic_vector ( 3 downto 0 ) |
FCT counter TX |
|
out |
std_logic_vector ( 2 downto 0 ) |
ACK counter RX |
|
out |
std_logic_vector ( 2 downto 0 ) |
NACK counter RX |
|
out |
std_logic_vector ( 3 downto 0 ) |
FCT counter RX |
|
out |
std_logic_vector ( 1 downto 0 ) |
FULL counter RX |
|
out |
std_logic_vector ( 1 downto 0 ) |
RETRY counter RX |
|
out |
std_logic_vector ( 7 downto 0 ) |
Current time slot |
|
out |
std_logic |
Reset configuration parameters control |
|
out |
std_logic |
Link has been reseted |
|
out |
std_logic_vector ( 7 downto 0 ) |
NACK Seq_num received |
|
out |
std_logic_vector ( 7 downto 0 ) |
ACK Seq_num received |
|
out |
std_logic |
Data received pulse signal |
|
out |
std_logic |
ACK received pulse signal |
|
out |
std_logic |
NACK received pulse signal |
|
out |
std_logic |
FCT received pulse signal |
|
out |
std_logic |
FULL received pulse signal |
|
out |
std_logic |
RETRY received pulse signal |