Back to Design Hierarchy Report

Entity - AXIS_SLAVE

Summary

Name	Location	Description
AXIS_SLAVE	AXIS_SLAVE.vhd#19

Instantiations

Count: 9

Name	Location	Description	Details
AXIS_SLAVE_inst	FIFO_DC_AXIS_S.vhd#162
AXIS_SLAVE_inst	FIFO_DC_AXIS_S.vhd#162
AXIS_SLAVE_inst	FIFO_DC_AXIS_S.vhd#162
AXIS_SLAVE_inst	FIFO_DC_AXIS_S.vhd#162
AXIS_SLAVE_inst	FIFO_DC_AXIS_S.vhd#162
AXIS_SLAVE_inst	FIFO_DC_AXIS_S.vhd#162
AXIS_SLAVE_inst	FIFO_DC_AXIS_S.vhd#162
AXIS_SLAVE_inst	FIFO_DC_AXIS_S.vhd#162
AXIS_SLAVE_inst	FIFO_DC_AXIS_S.vhd#162

Generics

Count: 3

Name	Type	Default value	Description
G_DWIDTH	integer	36	Total data width
S_AXIS_TDATA_WIDTH	integer	32	TData Width
S_AXIS_TUSER_WIDTH	integer	4	TUser Width

Ports

Count: 11

Name	Mode	Type	Description
wr_data	out	std_logic_vector ( G_DWIDTH - 1 downto 0 )	Data write bus
wr_enable	out	std_logic	Write enable
status_full	in	std_logic	Status indicating FIFO is full
status_busy_flush	in	std_logic	Status indicating FIFO is busy flushing
s00_axis_aclk	in	std_logic	AXI4Stream sink: Clock
s00_axis_aresetn	in	std_logic	AXI4Stream sink: Reset
s00_axis_tready	out	std_logic	Ready to accept data in
s00_axis_tdata	in	std_logic_vector ( S_AXIS_TDATA_WIDTH - 1 downto 0 )	Data input bus
s00_axis_tuser	in	std_logic_vector ( S_AXIS_TUSER_WIDTH - 1 downto 0 )	User-defined data input bus
s00_axis_tlast	in	std_logic	Indicates boundary of last packet
s00_axis_tvalid	in	std_logic	Data is valid

Back to Design Hierarchy Report