Entity - ppl_64_init_hssl

Summary

Name	Location	Description
ppl_64_init_hssl	ppl_64_init_hssl.vhd#32

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Count: 17

Name	Mode	Type	Description
RST_N	in	std_logic	Global reset, Active Low
CLK	in	std_logic	Clock generated by HSSL IP
RECEIVER_DISABLED_PLIF	in	std_logic	Flag to enable RX function of HSSL IP
CDR_PLIF	in	std_logic	Flag to enable CDR_PLIF function of HSSL IP
TRANSMITTER_DISABLED_PLIF	in	std_logic	Flag to enable TX function of HSSL IP
PLL_PMA_PWR_UP_PLIH	out	std_logic	‘0’- PLL is disabled. Dynamic power consumption is highly reduced. ‘1’ - PLL is active. Normal PLL operation
TX_DRIVER_PWRDWN_N_PLIH	out	std_logic	TX driver is powered down (TX lanes stay at high impedance) , when asserted. Active low
PLL_PMA_RST_N_PLIH	out	std_logic	Active-low PMA PLL reset
PLL_PMA_LOCK_ANALOG_HSSL	in	std_logic	PMA PLL is locked (Analog Signal)
TX_RST_N_PLIH	out	std_logic	TX PCS reset. Active low
TX_BUSY_HSSL	in	std_logic	Indicates that RX PCS is busy while being reset
RX_PMA_PWR_UP_PLIH	out	std_logic	Resets RX PLL and CDR, when asserted. Active low.
RX_PMA_RST_N_PLIH	out	std_logic	RX PCS reset. Active low
RX_PMA_LL_SLOW_LOCKED_HSSL	in	std_logic	Asserted when RX PMA Lead Lag (LL) PLL is locked.
RX_RST_N_PLIH	out	std_logic	PMA PLL power up
RX_BUSY_HSSL	in	std_logic	Indicates that RX PCS is busy while being reseted
HSSL_RESET_DONE_PLIH	out	std_logic	HSSL reset done flag