# Design Hierarchy
## Summary
| Hierarchy | Modules | Instantiations |
| :---: | --- | --- |
| 
| 35 | 103 |
## Dependencies
Properly architecture your design to tend to a highly hierarchical design. Modules that instantiate too many other modules have likely too many responsibilities.
| Instance | Modules | Instantiations |
| --- | --- | --- |
|inst_data_link|Count: 16
FIFO_DC_DROP_BAD_FRAME
data_crc_check
data_crc_compute
data_desencapsulation
data_desencapsulation_bc
data_encapsulation
data_err_management
data_in_bc_buf
data_in_buf
data_link_reset
data_mac
data_out_bc_buf
data_out_buff
data_seq_check
data_seq_compute
data_word_id_fsm|Count: 31
gen_data_in_buff(0)\.inst_data_in_buf: data_in_buf (rtl)
gen_data_in_buff(1)\.inst_data_in_buf: data_in_buf (rtl)
gen_data_in_buff(2)\.inst_data_in_buf: data_in_buf (rtl)
gen_data_in_buff(3)\.inst_data_in_buf: data_in_buf (rtl)
gen_data_in_buff(4)\.inst_data_in_buf: data_in_buf (rtl)
gen_data_in_buff(5)\.inst_data_in_buf: data_in_buf (rtl)
gen_data_in_buff(6)\.inst_data_in_buf: data_in_buf (rtl)
gen_data_in_buff(7)\.inst_data_in_buf: data_in_buf (rtl)
gen_data_out_buff(0)\.inst_data_out_buff: data_out_buff (rtl)
gen_data_out_buff(1)\.inst_data_out_buff: data_out_buff (rtl)
gen_data_out_buff(2)\.inst_data_out_buff: data_out_buff (rtl)
gen_data_out_buff(3)\.inst_data_out_buff: data_out_buff (rtl)
gen_data_out_buff(4)\.inst_data_out_buff: data_out_buff (rtl)
gen_data_out_buff(5)\.inst_data_out_buff: data_out_buff (rtl)
gen_data_out_buff(6)\.inst_data_out_buff: data_out_buff (rtl)
gen_data_out_buff(7)\.inst_data_out_buff: data_out_buff (rtl)
inst_data_crc_check: data_crc_check (rtl)
inst_data_crc_compute: data_crc_compute (rtl)
inst_data_desencapsulation: data_desencapsulation (rtl)
inst_data_desencapsulation_bc: data_desencapsulation_bc (rtl)
inst_data_encapsulation: data_encapsulation (rtl)
inst_data_err_management: data_err_management (Behavioral)
inst_data_in_bc_buf: data_in_bc_buf (rtl)
inst_data_link_reset: data_link_reset (rtl)
inst_data_mac: data_mac (rtl)
inst_data_out_bc_buf: data_out_bc_buf (rtl)
inst_data_seq_check: data_seq_check (rtl)
inst_data_seq_compute: data_seq_compute (rtl)
inst_data_word_id_fsm: data_word_id_fsm (rtl)
inst_mid_buf: FIFO_DC_DROP_BAD_FRAME (RTL)
inst_mid_buf_bc: FIFO_DC_DROP_BAD_FRAME (RTL)
|
|spacefibre_light_top (top)|Count: 7
demux_rx
mux_tx
reset_gen
data_link
mib_data_link
mib_phy_plus_lane
phy_plus_lane|Count: 7
inst_data_link: data_link (Behavioral)
inst_demux_rx: demux_rx (rtl)
inst_mib_data_link: mib_data_link (rtl)
inst_mib_phy_plus_lane: mib_phy_plus_lane (rtl)
inst_mux_tx: mux_tx (rtl)
inst_phy_plus_lane: phy_plus_lane (rtl)
inst_reset_sync_clk_from_GTY: reset_gen (rtl)
|
|inst_phy_plus_lane|Count: 7
FIFO_DC
lane_ctrl_word_detect
lane_ctrl_word_insert
lane_init_fsm
parallel_loopback
rx_sync_fsm
skip_insertion|Count: 10
inst_fifo_in_ctrl: FIFO_DC (RTL)
inst_fifo_out_ctrl: FIFO_DC (RTL)
inst_fifo_rx_data: FIFO_DC (RTL)
inst_fifo_tx_data: FIFO_DC (RTL)
inst_lane_ctrl_word_detect: lane_ctrl_word_detect (rtl)
inst_lane_ctrl_word_insert: lane_ctrl_word_insert (rtl)
inst_lane_init_fsm: lane_init_fsm (rtl)
inst_parallel_loopback: parallel_loopback (rtl)
inst_rx_sync_fsm: rx_sync_fsm (rtl)
inst_skip_insertion: skip_insertion (rtl)
|
|ints_fifo_dc_axis_m|Count: 2
FIFO_DC
AXIS_MASTER|Count: 2
AXIS_MASTER_inst: AXIS_MASTER (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_m|Count: 2
FIFO_DC
AXIS_MASTER|Count: 2
AXIS_MASTER_inst: AXIS_MASTER (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_m|Count: 2
FIFO_DC
AXIS_MASTER|Count: 2
AXIS_MASTER_inst: AXIS_MASTER (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_m|Count: 2
FIFO_DC
AXIS_MASTER|Count: 2
AXIS_MASTER_inst: AXIS_MASTER (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_m|Count: 2
FIFO_DC
AXIS_MASTER|Count: 2
AXIS_MASTER_inst: AXIS_MASTER (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_m|Count: 2
FIFO_DC
AXIS_MASTER|Count: 2
AXIS_MASTER_inst: AXIS_MASTER (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_m|Count: 2
FIFO_DC
AXIS_MASTER|Count: 2
AXIS_MASTER_inst: AXIS_MASTER (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_m|Count: 2
FIFO_DC
AXIS_MASTER|Count: 2
AXIS_MASTER_inst: AXIS_MASTER (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_m|Count: 2
FIFO_DC
AXIS_MASTER|Count: 2
AXIS_MASTER_inst: AXIS_MASTER (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_s|Count: 2
FIFO_DC
AXIS_SLAVE|Count: 2
AXIS_SLAVE_inst: AXIS_SLAVE (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_s|Count: 2
FIFO_DC
AXIS_SLAVE|Count: 2
AXIS_SLAVE_inst: AXIS_SLAVE (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_s|Count: 2
FIFO_DC
AXIS_SLAVE|Count: 2
AXIS_SLAVE_inst: AXIS_SLAVE (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_s|Count: 2
FIFO_DC
AXIS_SLAVE|Count: 2
AXIS_SLAVE_inst: AXIS_SLAVE (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_s|Count: 2
FIFO_DC
AXIS_SLAVE|Count: 2
AXIS_SLAVE_inst: AXIS_SLAVE (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_s|Count: 2
FIFO_DC
AXIS_SLAVE|Count: 2
AXIS_SLAVE_inst: AXIS_SLAVE (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_s|Count: 2
FIFO_DC
AXIS_SLAVE|Count: 2
AXIS_SLAVE_inst: AXIS_SLAVE (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_s|Count: 2
FIFO_DC
AXIS_SLAVE|Count: 2
AXIS_SLAVE_inst: AXIS_SLAVE (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|ints_fifo_dc_axis_s|Count: 2
FIFO_DC
AXIS_SLAVE|Count: 2
AXIS_SLAVE_inst: AXIS_SLAVE (implementation)
fifo_dc_inst: FIFO_DC (RTL)
|
|gen_data_in_buff(0)\.inst_data_in_buf|Count: 1
FIFO_DC_AXIS_M|Count: 1
ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
|
|gen_data_in_buff(1)\.inst_data_in_buf|Count: 1
FIFO_DC_AXIS_M|Count: 1
ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
|
|gen_data_in_buff(2)\.inst_data_in_buf|Count: 1
FIFO_DC_AXIS_M|Count: 1
ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
|
|gen_data_in_buff(3)\.inst_data_in_buf|Count: 1
FIFO_DC_AXIS_M|Count: 1
ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
|
|gen_data_in_buff(4)\.inst_data_in_buf|Count: 1
FIFO_DC_AXIS_M|Count: 1
ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
|
|gen_data_in_buff(5)\.inst_data_in_buf|Count: 1
FIFO_DC_AXIS_M|Count: 1
ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
|
|gen_data_in_buff(6)\.inst_data_in_buf|Count: 1
FIFO_DC_AXIS_M|Count: 1
ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
|
|gen_data_in_buff(7)\.inst_data_in_buf|Count: 1
FIFO_DC_AXIS_M|Count: 1
ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
|
|gen_data_out_buff(0)\.inst_data_out_buff|Count: 1
FIFO_DC_AXIS_S|Count: 1
ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
|
|gen_data_out_buff(1)\.inst_data_out_buff|Count: 1
FIFO_DC_AXIS_S|Count: 1
ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
|
|gen_data_out_buff(2)\.inst_data_out_buff|Count: 1
FIFO_DC_AXIS_S|Count: 1
ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
|
|gen_data_out_buff(3)\.inst_data_out_buff|Count: 1
FIFO_DC_AXIS_S|Count: 1
ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
|
|gen_data_out_buff(4)\.inst_data_out_buff|Count: 1
FIFO_DC_AXIS_S|Count: 1
ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
|
|gen_data_out_buff(5)\.inst_data_out_buff|Count: 1
FIFO_DC_AXIS_S|Count: 1
ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
|
|gen_data_out_buff(6)\.inst_data_out_buff|Count: 1
FIFO_DC_AXIS_S|Count: 1
ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
|
|gen_data_out_buff(7)\.inst_data_out_buff|Count: 1
FIFO_DC_AXIS_S|Count: 1
ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
|
|inst_data_in_bc_buf|Count: 1
FIFO_DC_AXIS_M|Count: 1
ints_fifo_dc_axis_m: FIFO_DC_AXIS_M (arch_imp)
|
|inst_data_out_bc_buf|Count: 1
FIFO_DC_AXIS_S|Count: 1
ints_fifo_dc_axis_s: FIFO_DC_AXIS_S (arch_imp)
|
|AXIS_MASTER_inst|||
|AXIS_MASTER_inst|||
|AXIS_MASTER_inst|||
|AXIS_MASTER_inst|||
|AXIS_MASTER_inst|||
|AXIS_MASTER_inst|||
|AXIS_MASTER_inst|||
|AXIS_MASTER_inst|||
|AXIS_MASTER_inst|||
|AXIS_SLAVE_inst|||
|AXIS_SLAVE_inst|||
|AXIS_SLAVE_inst|||
|AXIS_SLAVE_inst|||
|AXIS_SLAVE_inst|||
|AXIS_SLAVE_inst|||
|AXIS_SLAVE_inst|||
|AXIS_SLAVE_inst|||
|AXIS_SLAVE_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|fifo_dc_inst|||
|inst_data_crc_check|||
|inst_data_crc_compute|||
|inst_data_desencapsulation|||
|inst_data_desencapsulation_bc|||
|inst_data_encapsulation|||
|inst_data_err_management|||
|inst_data_link_reset|||
|inst_data_mac|||
|inst_data_seq_check|||
|inst_data_seq_compute|||
|inst_data_word_id_fsm|||
|inst_demux_rx|||
|inst_fifo_in_ctrl|||
|inst_fifo_out_ctrl|||
|inst_fifo_rx_data|||
|inst_fifo_tx_data|||
|inst_lane_ctrl_word_detect|||
|inst_lane_ctrl_word_insert|||
|inst_lane_init_fsm|||
|inst_mib_data_link|||
|inst_mib_phy_plus_lane|||
|inst_mid_buf|||
|inst_mid_buf_bc|||
|inst_mux_tx|||
|inst_parallel_loopback|||
|inst_reset_sync_clk_from_GTY|||
|inst_rx_sync_fsm|||
|inst_skip_insertion|||
Note that instantiations from blackboxes or third-party IPs are not listed in this report.
## VHDL Entities
Count: 50
| Name | Location | Description | Details |
| --- | --- | --- | :---: |
|AXIS_MASTER|AXIS_MASTER.vhd#19||[
](design/module_1.md)|
|AXIS_SLAVE|AXIS_SLAVE.vhd#19||[](design/module_2.md)|
|FIFO_DC|fifo_dc.vhd#36||[](design/module_3.md)|
|FIFO_DC_AXIS_M|FIFO_DC_AXIS_M.vhd#36||[](design/module_4.md)|
|FIFO_DC_AXIS_S|FIFO_DC_AXIS_S.vhd#36||[](design/module_5.md)|
|FIFO_DC_DROP_BAD_FRAME|fifo_dc_drop_bad_frame.vhd#36||[](design/module_6.md)|
|data_crc_check|data_crc_check.vhd#32||[](design/module_7.md)|
|data_crc_check_tb|data_crc_check_tb.vhd#22||[](design/module_8.md)|
|data_crc_compute|data_crc_compute.vhd#32||[](design/module_9.md)|
|data_desencapsulation|data_desencapsulation.vhd#32||[](design/module_10.md)|
|data_desencapsulation_bc|data_desencapsulation_bc.vhd#32||[](design/module_11.md)|
|data_encapsulation|data_encapsulation.vhd#32||[](design/module_12.md)|
|data_err_management|data_err_management.vhd#32||[](design/module_13.md)|
|data_in_bc_buf|data_in_bc_buf.vhd#32||[](design/module_14.md)|
|data_in_buf|data_in_buf.vhd#33||[](design/module_15.md)|
|data_link|data_link.vhd#31||[](design/module_16.md)|
|data_link_reset|data_link_reset.vhd#32||[](design/module_17.md)|
|data_mac|data_mac.vhd#32||[](design/module_18.md)|
|data_out_bc_buf|data_out_bc_buf.vhd#32||[](design/module_19.md)|
|data_out_buff|data_out_buf.vhd#33||[](design/module_20.md)|
|data_seq_check|data_seq_check.vhd#32||[](design/module_21.md)|
|data_seq_compute|data_seq_compute.vhd#32||[](design/module_22.md)|
|data_word_id_fsm|data_word_id_fsm.vhd#32||[](design/module_23.md)|
|demux_rx|demux_rx.vhd#32||[](design/module_24.md)|
|lane_ctrl_word_detect|lane_ctrl_word_detect.vhd#33||[](design/module_25.md)|
|lane_ctrl_word_insert|lane_ctrl_word_insert.vhd#33||[](design/module_26.md)|
|lane_init_fsm|lane_init_fsm.vhd#32||[](design/module_27.md)|
|mib_data_link|mib_data_link.vhd#29||[](design/module_28.md)|
|mib_phy_plus_lane|mib_phy_plus_lane.vhd#32||[](design/module_29.md)|
|mux_tx|mux_tx.vhd#32||[](design/module_30.md)|
|parallel_loopback|parallel_loopback.vhd#32||[](design/module_31.md)|
|phy_plus_lane|phy_plus_lane.vhd#41||[](design/module_32.md)|
|reset_gen|reset_gen.vhd#30||[](design/module_33.md)|
|rx_sync_fsm|rx_sync_fsm.vhd#32||[](design/module_34.md)|
|skip_insertion|skip_insertion.vhd#33||[](design/module_35.md)|
|spacefibre_light_top|spacefibre_light_top.vhd#39||[](design/module_36.md)|
|spacefibre_light_top_ip|spacefibre_light_top_ip.vhd#36||[](design/module_37.md)|
|subpart_tb|subpart_tb.vhd#22||[](design/module_38.md)|
|tb_data_desencapsulation|tb_data_desencapsulation.vhd#22||[](design/module_39.md)|
|tb_data_in_buf|data_in_buf_tb.vhd#19||[](design/module_40.md)|
|tb_data_mac|data_mac_tb.vhd#22||[](design/module_41.md)|
|tb_data_out_buff|data_out_buf_tb.vhd#22||[](design/module_42.md)|
|tb_fifo_dc|tb_fifo_dc.vhd#7||[](design/module_43.md)|
|tb_fifo_dc_axis_to_custom|tb_fifo_dc_axis_to_custom.vhd#34||[](design/module_44.md)|
|tb_fifo_dc_custom_to_axis|tb_fifo_dc_custom_to_axis.vhd#16||[](design/module_45.md)|
|tb_fifo_dc_drop_bad_frame|tb_fifo_dc_drop_bad_frame.vhd#7||[](design/module_46.md)|
|tb_lane_ctrl_word_insert|tb_lane_ctrl_word_insert.vhd#7||[](design/module_47.md)|
|tb_lane_init_fsm|tb_lane_init_fsm.vhd#7||[](design/module_48.md)|
|tb_receive_error|tb_receive_error.vhd#21||[](design/module_49.md)|
|tb_rx_sync_fsm|tb_rx_sync_fsm.vhd#7||[](design/module_50.md)|
## VHDL Packages
Count: 3
| Name | Location | Description | Details |
| --- | --- | --- | :---: |
|PKG_TOOLS|pkg_tools.vhd#47||[](design/package_1.md)|
|data_link_lib|pkg_data_link.vhd#32||[](design/package_2.md)|
|pkg_phy_plus_lane|pkg_phy_plus_lane.vhd#34||[](design/package_3.md)|