Back to Design Hierarchy Report

Entity - data_crc_compute

Summary

Name	Location	Description
data_crc_compute	data_crc_compute.vhd#32

Instantiations

Count: 1

Name	Location	Description	Details
inst_data_crc_compute	data_link.vhd#1158

Generics

Count: 0

Ports

Count: 12

Name	Mode	Type	Description
CLK	in	std_logic	Global Clock
LINK_RESET_DLRE	in	std_logic	Link Reset command
LANE_ACTIVE_PPL	in	std_logic	Lane Active flag for the DATA Link Layer
NEW_WORD_DSCOM	in	std_logic	New word flag associated with DATA_DSCOM
DATA_DSCOM	in	std_logic_vector ( C_DATA_LENGTH - 1 downto 0 )	Data parallel from data_seq_compute
VALID_K_CHARAC_DSCOM	in	std_logic_vector ( C_BYTE_BY_WORD_LENGTH - 1 downto 0 )	K charachter valid in the 32-bit DATA_DSCOM vector
TYPE_FRAME_DSCOM	in	std_logic_vector ( C_TYPE_FRAME_LENGTH - 1 downto 0 )	Type of the frame associated with DATA_DSCOM
END_FRAME_DSCOM	in	std_logic	End frame/control word associated with DATA_DSCOM
FIFO_FULL_TX_LANE	in	std_logic	Fifo TX full flag from the lane layer
VALID_K_CHARAC_DCCOM	out	std_logic_vector ( C_BYTE_BY_WORD_LENGTH - 1 downto 0 )	Data parallel to lane layer
DATA_DCCOM	out	std_logic_vector ( C_DATA_LENGTH - 1 downto 0 )	K charachter valid in the 32-bit DATA_DCCOM vector
NEW_WORD_DCCOM	out	std_logic	New word Flag associated with DATA_DCCOM

Back to Design Hierarchy Report