Entity - data_in_buf

Summary

Name	Location	Description
data_in_buf	data_in_buf.vhd#33

Count: 8

Name	Location	Description	Details
gen_data_in_buff(0).inst_data_in_buf	data_link.vhd#803
gen_data_in_buff(1).inst_data_in_buf	data_link.vhd#803
gen_data_in_buff(2).inst_data_in_buf	data_link.vhd#803
gen_data_in_buff(3).inst_data_in_buf	data_link.vhd#803
gen_data_in_buff(4).inst_data_in_buf	data_link.vhd#803
gen_data_in_buff(5).inst_data_in_buf	data_link.vhd#803
gen_data_in_buff(6).inst_data_in_buf	data_link.vhd#803
gen_data_in_buff(7).inst_data_in_buf	data_link.vhd#803

Count: 0

Count: 16

Name	Mode	Type	Description
RST_N	in	std_logic	Global reset (Active-low)
CLK	in	std_logic	Global Clock
LINK_RESET_DLRE	in	std_logic	Link Reset command
LINK_RESET_DIBUF	out	std_logic	Link Reset request to data_link_reset
M_AXIS_ARSTN_NW	in	std_logic	Active-low asynchronous reset for the AXI-Stream interface
M_AXIS_ACLK_NW	in	std_logic	Clock signal for the AXI-Stream interface
M_AXIS_TVALID_DIBUF	out	std_logic	Indicates that TDATA, TUSER, and TLAST are valid
M_AXIS_TDATA_DIBUF	out	std_logic_vector ( C_DATA_LENGTH - 1 downto 0 )	AXI-Stream data bus
M_AXIS_TLAST_DIBUF	out	std_logic	Indicates the end of a data packet
M_AXIS_TREADY_NW	in	std_logic	Receiver ready signal (slave is ready to accept data)
M_AXIS_TUSER_DIBUF	out	std_logic_vector ( C_BYTE_BY_WORD_LENGTH - 1 downto 0 )	AXI-Stream user-defined sideband signal
DATA_DDES	in	std_logic_vector ( C_DATA_K_WIDTH - 1 downto 0 )	Data parallel (K character + DATA) from data_desencapsulation
DATA_EN_DDES	in	std_logic	Data valid flag associated with DATA_DDES
REQ_FCT_DIBUF	out	std_logic	FCT request to data_mac
REQ_FCT_DONE_DMAC	in	std_logic	FCT request done flag from data_mac
INPUT_BUF_OVF_DIBUF	out	std_logic	Input buffer oveflow flag