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Entity - reset_gen

Summary

Name

Location

Description

reset_gen

reset_gen.vhd#30

Instantiations

Count: 1

Name

Location

Description

Details

inst_reset_sync_clk_from_GTY

spacefibre_light_top.vhd#556

View Instantiation Details

Generics

Count: 0

Ports

Count: 5

Name

Mode

Type

Description

RST_N

in

std_logic

global reset

CLK

in

std_logic

General clock

RST_TX_DONE

in

std_logic

Reset tx of IP GTY done flag

LANE_RESET

in

std_logic

LANE RESET command

INTERNAL_SYNC_RST_N

out

std_logic

Internal reset resynchronized on 150MHz internal clock


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