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Entity - ppl_64_bus_concat_tx

Summary

Name	Location	Description
ppl_64_bus_concat_tx	ppl_64_bus_concat_tx.vhd#32

Instantiations

Count: 1

Name	Location	Description	Details
inst_ppl_64_bus_concat_tx	phy_plus_lane_64b.vhd#696

Generics

Count: 0

Ports

Count: 12

Name	Mode	Type	Description
RST_N	in	std_logic	global reset
CLK	in	std_logic	Clock synchronous with the Data-Link Layer
DATA_TX_DL	in	std_logic_vector ( 31 downto 0 )	32-bit data parallel to be sent from Data-Link Layer
NEW_DATA_TX_DL	in	std_logic	New data flag
VALID_K_CHARAC_TX_DL	in	std_logic_vector ( 3 downto 0 )	4-bit valid K character flags from Data-link layer
CAPABILITY_TX_DL	in	std_logic_vector ( 7 downto 0 )	Capability field sent in INIT3 control word
LANE_RESET_DL	in	std_logic	Lane reset command from Data-Link Layer
DATA_TX_PLBCT	out	std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )	64-bit Data parallel to be sent
NEW_DATA_TX_PLBCT	out	std_logic	New data flag
VALID_K_CHARAC_TX_PLBCT	out	std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )	8-bit valid K character flags
CAPABILITY_TX_PLBCT	out	std_logic_vector ( 7 downto 0 )	Capability field sent in INIT3 control word
LANE_RESET_PLBCT	out	std_logic	Lane reset command

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