[Back to Design Hierarchy Report](../design_hierarchy.md#vhdl-entities)
# Entity - skip_insertion
## Summary
| Name | Location | Description |
| --- | --- | --- |
|skip_insertion|skip_insertion.vhd#33||
## Instantiations
Count: 1
| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| inst_skip_insertion | phy_plus_lane.vhd#815 | | [
](module_35/instantiation_1.md) |
## Generics
Count: 0
## Ports
Count: 9
| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|RST_N|in|std_logic|global reset|
|CLK|in|std_logic|Clock generated by GTY IP|
|NEW_DATA_FROM_LCWI|in|std_logic|New data Flag|
|DATA_TX_FROM_LCWI|in|std_logic_vector ( 31 downto 00 )|Data 64-bit receive from DATA_LINK layer|
|VALID_K_CHARAC_FROM_LCWI|in|std_logic_vector ( 03 downto 00 )|Flags indicates which byte is a K character from DATA-LINK layer|
|WAIT_SEND_DATA|out|std_logic|Flag to indicates that the lane_ctrl_word_insert send a SKIP control word|
|DATA_TX_TO_IP|out|std_logic_vector ( 31 downto 00 )|Data 64-bit send to manufacturer IP|
|VALID_K_CHARAC_TO_IP|out|std_logic_vector ( 03 downto 00 )|Flags indicates which byte is a K character|
|ENABLE_TRANSM_DATA|in|std_logic|Flag to enable to send data|
[Back to Design Hierarchy Report](../design_hierarchy.md#vhdl-entities)