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Entity - ppl_64_bus_split_rx

Summary

Name	Location	Description
ppl_64_bus_split_rx	ppl_64_bus_split_rx.vhd#33

Instantiations

Count: 0

Generics

Count: 0

Ports

Count: 16

Name	Mode	Type	Description
RST_N	in	std_logic	global reset
CLK	in	std_logic	Clock synchronous of the Data-link layer
FIFO_RX_RD_EN_DL	in	std_logic	FIFO RX read enable flag from the Data-link layer
DATA_RX_PLBSR	out	std_logic_vector ( 31 downto 0 )	32-bit Data parallel
FIFO_RX_DATA_VALID_PLBSR	out	std_logic	Flag new data
VALID_K_CHARAC_RX_PLBSR	out	std_logic_vector ( 3 downto 0 )	4-bit valid K character
FAR_END_CAPA_PLBSR	out	std_logic_vector ( 7 downto 0 )	Capability field received in INIT3 control word
LANE_ACTIVE_PLBSR	out	std_logic	Lane Active flag
FIFO_RX_RD_EN_PLBSR	out	std_logic	FIFO RX read enable flag
DATA_RX_PLFRD	in	std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )	64-bit Data parallel
FIFO_RX_DATA_VALID_PLFRD	in	std_logic	Flag new data
FIFO_RX_EMPTY_PLFRD	in	std_logic	Flag FIFO Empty
VALID_K_CHARAC_RX_PLFRD	in	std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )	8-bit valid K character flags
DATA_RDY_RX_PLFRD	in	std_logic_vector ( 1 downto 0 )	Data valid flag
FAR_END_CAPA_PLFRC	in	std_logic_vector ( 7 downto 0 )	Capability field received in INIT3 control word
LANE_ACTIVE_PLFRC	in	std_logic	Lane Active flag

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