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Entity - parallel_loopback

Summary

Name	Location	Description
parallel_loopback	parallel_loopback.vhd#32

Instantiations

Count: 1

Name	Location	Description	Details
inst_parallel_loopback	phy_plus_lane.vhd#834

Generics

Count: 0

Ports

Count: 13

Name	Mode	Type	Description
CLK	in	std_logic	Clock generated by GTY IP
RST_N	in	std_logic	Global reset
DATA_TX_FROM_LCWI	in	std_logic_vector ( 31 downto 00 )	32-bit Data
VALID_K_CARAC_FROM_LCWI	in	std_logic_vector ( 03 downto 00 )	4-bit Valid K character
DATA_RDY_FROM_LCWI	in	std_logic	Data ready flag
DATA_TX_FROM_RSF	in	std_logic_vector ( 31 downto 00 )	32-bit Data
VALID_K_CARAC_FROM_RSF	in	std_logic_vector ( 03 downto 00 )	4-bit Valid K character
DATA_RDY_FROM_RSF	in	std_logic	Data ready flag
WAIT_SKIP_DATA	in	std_logic	Wait for data to be skip
DATA_TX_TO_LCWD	out	std_logic_vector ( 31 downto 00 )	32-bit Data
VALID_K_CARAC_TO_LCWD	out	std_logic_vector ( 03 downto 00 )	4-bit Valid K character
DATA_RDY_TO_LCWD	out	std_logic	Data ready flag
PARALLEL_LOOPBACK_EN	in	std_logic	Enable or disable the parallel loopback for the lane

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