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# Entity - parallel_loopback

## Summary

| Name | Location | Description |
| --- | --- | --- |
|parallel_loopback|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#32">parallel_loopback.vhd#32</linty-anchor>||
## Instantiations

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| inst_parallel_loopback | <linty-anchor href="/src/module_phy_plus_lane/phy_plus_lane.vhd#834">phy_plus_lane.vhd#834</linty-anchor> |  | [<img title="View Instantiation Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Instantiation Details">](module_31/instantiation_1.md) |


## Generics

Count: 0

## Ports

Count: 13

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#34">CLK</linty-anchor>|in|std_logic|Clock generated by GTY IP|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#35">RST_N</linty-anchor>|in|std_logic|Global reset|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#37">DATA_TX_FROM_LCWI</linty-anchor>|in|std_logic_vector ( 31 downto 00 )|32-bit Data|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#38">VALID_K_CARAC_FROM_LCWI</linty-anchor>|in|std_logic_vector ( 03 downto 00 )|4-bit Valid K character|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#39">DATA_RDY_FROM_LCWI</linty-anchor>|in|std_logic|Data ready flag|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#41">DATA_TX_FROM_RSF</linty-anchor>|in|std_logic_vector ( 31 downto 00 )|32-bit Data|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#42">VALID_K_CARAC_FROM_RSF</linty-anchor>|in|std_logic_vector ( 03 downto 00 )|4-bit Valid K character|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#43">DATA_RDY_FROM_RSF</linty-anchor>|in|std_logic|Data ready flag|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#45">WAIT_SKIP_DATA</linty-anchor>|in|std_logic|Wait for data to be skip|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#47">DATA_TX_TO_LCWD</linty-anchor>|out|std_logic_vector ( 31 downto 00 )|32-bit Data|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#48">VALID_K_CARAC_TO_LCWD</linty-anchor>|out|std_logic_vector ( 03 downto 00 )|4-bit Valid K character|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#49">DATA_RDY_TO_LCWD</linty-anchor>|out|std_logic|Data ready flag|
|<linty-anchor href="//src/module_phy_plus_lane/parallel_loopback.vhd#51">PARALLEL_LOOPBACK_EN</linty-anchor>|in|std_logic|Enable or disable the parallel loopback for the lane|


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