spacefibrelight
Summary Report
Design Hierarchy
Summary
Dependencies
VHDL Entities
VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Finite State Machines (FSM)
Combinational Loops
Latches
spacefibrelight
Entity - tb_ppl_64_bus_split_rx
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Entity - tb_ppl_64_bus_split_rx
Summary
Name
Location
Description
tb_ppl_64_bus_split_rx
tb_ppl_64_split_rx.vhd#34
Instantiations
Count: 0
Generics
Count: 0
Ports
Count: 0