Entity - FIFO_DC_AXIS_M

Summary

Name	Location	Description
FIFO_DC_AXIS_M	FIFO_DC_AXIS_M.vhd#36

Count: 9

Name	Location	Description	Details
ints_fifo_dc_axis_m	data_in_bc_buf.vhd#121
ints_fifo_dc_axis_m	data_in_buf.vhd#157
ints_fifo_dc_axis_m	data_in_buf.vhd#157
ints_fifo_dc_axis_m	data_in_buf.vhd#157
ints_fifo_dc_axis_m	data_in_buf.vhd#157
ints_fifo_dc_axis_m	data_in_buf.vhd#157
ints_fifo_dc_axis_m	data_in_buf.vhd#157
ints_fifo_dc_axis_m	data_in_buf.vhd#157
ints_fifo_dc_axis_m	data_in_buf.vhd#157

Count: 6

Name	Type	Default value	Description
G_DWIDTH	integer	36	Data bus FIFO length
G_AWIDTH	integer	10	Address bus FIFO length
G_THRESHOLD_HIGH	integer	2**10	High threshold
G_THRESHOLD_LOW	integer	0	Low threshold
M_AXIS_TDATA_WIDTH	integer	32	Data AXIS length
M_AXIS_TUSER_WIDTH	integer	4	User AXIS length

Count: 18

Name	Mode	Type	Description
aresetn	in	std_logic	Active-low reset
WR_CLK	in	std_logic	Clock
WR_DATA	in	std_logic_vector ( G_DWIDTH - 1 downto 0 )	Data write bus
WR_DATA_EN	in	std_logic	Write command
CMD_FLUSH	in	std_logic	FIFO flush command
STATUS_BUSY_FLUSH	out	std_logic	FIFO is flushing
STATUS_THRESHOLD_HIGH	out	std_logic	High threshold reached flag (on WR_CLK)
STATUS_THRESHOLD_LOW	out	std_logic	Low threshold reached flag (on RD_CLK)
STATUS_FULL	out	std_logic	Full FIFO flag (on WR_CLK)
STATUS_EMPTY	out	std_logic	Empty FIFO flag (on RD_CLK)
STATUS_LEVEL_WR	out	std_logic_vector ( G_AWIDTH - 1 downto 0 )	FIFO fill level (on WR_CLK)
STATUS_LEVEL_RD	out	std_logic_vector ( G_AWIDTH - 1 downto 0 )	FIFO fill level (on RD_CLK)
M_AXIS_ACLK	in	std_logic	Clock input for the AXI Stream Master interface
M_AXIS_TVALID	out	std_logic	Indicates that the data on M_AXIS_TDATA is valid
M_AXIS_TDATA	out	std_logic_vector ( M_AXIS_TDATA_WIDTH - 1 downto 0 )	Data output bus for the AXI Stream Master interface
M_AXIS_TLAST	out	std_logic	Indicates the last transfer in a packet
M_AXIS_TREADY	in	std_logic	Indicates that the receiver is ready to accept data
M_AXIS_TUSER	out	std_logic_vector ( M_AXIS_TUSER_WIDTH - 1 downto 0 )	User-defined data output bus for the AXI Stream Master interface