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Entity - ppl_64_parallel_loopback

Summary

Name	Location	Description
ppl_64_parallel_loopback	ppl_64_parallel_loopback.vhd#32

Instantiations

Count: 0

Generics

Count: 0

Ports

Count: 15

Name	Mode	Type	Description
CLK	in	std_logic	Clock generated by HSSL IP
RST_N	in	std_logic	Global reset. Active low
DATA_TX_PLCWI	in	std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )	64-bit Data
VALID_K_CARAC_PLCWI	in	std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )	8-bit Valid K character
DATA_RDY_PLCWI	in	std_logic	Data ready flag
DATA_TX_PLRSF	in	std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )	64-bit Data
VALID_K_CARAC_PLRSF	in	std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )	8-bit Valid K character
DATA_RDY_PLRSF	in	std_logic	Data ready flag
LOSS_OF_SIGNAL_PLRSF	in	std_logic	Loss of signal flag from PLRSF
WAIT_SEND_DATA_PLSI	in	std_logic	Wait send data signal for SKIP insertion
DATA_RX_PLPL	out	std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )	64-bit Data
VALID_K_CHARAC_PLPL	out	std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )	8-bit Valid K character
DATA_RDY_PLPL	out	std_logic	Data ready flag
LOSS_OF_SIGNAL_PLPL	out	std_logic	Loss of signal flag from PLPL
PARALLEL_LOOPBACK_EN_MIB	in	std_logic	Enable or disable the parallel loopback

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