Entity - FIFO_DC_AXIS_S

Summary

Name	Location	Description
FIFO_DC_AXIS_S	FIFO_DC_AXIS_S.vhd#36

Count: 9

Name	Location	Description	Details
ints_fifo_dc_axis_s	data_out_bc_buf.vhd#133
ints_fifo_dc_axis_s	data_out_buf.vhd#186
ints_fifo_dc_axis_s	data_out_buf.vhd#186
ints_fifo_dc_axis_s	data_out_buf.vhd#186
ints_fifo_dc_axis_s	data_out_buf.vhd#186
ints_fifo_dc_axis_s	data_out_buf.vhd#186
ints_fifo_dc_axis_s	data_out_buf.vhd#186
ints_fifo_dc_axis_s	data_out_buf.vhd#186
ints_fifo_dc_axis_s	data_out_buf.vhd#186

Count: 6

Name	Type	Default value	Description
G_DWIDTH	integer	36	Data bus FIFO length
G_AWIDTH	integer	10	Address bus FIFO length
G_THRESHOLD_HIGH	integer	2**10	High threshold
G_THRESHOLD_LOW	integer	0	Low threshold
S_AXIS_TDATA_WIDTH	integer	32	Data AXIS length
S_AXIS_TUSER_WIDTH	integer	4	User AXIS length

Count: 19

Name	Mode	Type	Description
aresetn	in	std_logic	Active-low reset
RD_CLK	in	std_logic	Clock
RD_DATA	out	std_logic_vector ( G_DWIDTH - 1 downto 0 )	Data read bus
RD_DATA_EN	in	std_logic	Read command
RD_DATA_VLD	out	std_logic	Data valid
CMD_FLUSH	in	std_logic	FIFO flush command
STATUS_BUSY_FLUSH	out	std_logic	FIFO is flushing
STATUS_THRESHOLD_HIGH	out	std_logic	High threshold reached flag (on WR_CLK)
STATUS_THRESHOLD_LOW	out	std_logic	Low threshold reached flag (on RD_CLK)
STATUS_FULL	out	std_logic	Full FIFO flag (on WR_CLK)
STATUS_EMPTY	out	std_logic	Empty FIFO flag (on RD_CLK)
STATUS_LEVEL_WR	out	std_logic_vector ( G_AWIDTH - 1 downto 0 )	FIFO fill level (on WR_CLK)
STATUS_LEVEL_RD	out	std_logic_vector ( G_AWIDTH - 1 downto 0 )	FIFO fill level (on RD_CLK)
S_AXIS_ACLK	in	std_logic	AXI4Stream Clock
S_AXIS_TREADY	out	std_logic	Ready to accept data
S_AXIS_TDATA	in	std_logic_vector ( S_AXIS_TDATA_WIDTH - 1 downto 0 )	Data input bus
S_AXIS_TUSER	in	std_logic_vector ( S_AXIS_TUSER_WIDTH - 1 downto 0 )	User-defined data input bus
S_AXIS_TLAST	in	std_logic	Indicates boundary of last packet
S_AXIS_TVALID	in	std_logic	Data is valid