Back to Design Hierarchy Report
Entity - FIFO_DC
Summary
Name |
Location |
Description |
---|---|---|
FIFO_DC |
Instantiations
Count: 22
Name |
Location |
Description |
Details |
---|---|---|---|
fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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fifo_dc_inst |
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inst_fifo_in_ctrl |
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inst_fifo_tx_data |
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inst_fifo_rx_data |
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inst_fifo_out_ctrl |
Generics
Count: 4
Name |
Type |
Default value |
Description |
---|---|---|---|
integer |
8 |
||
integer |
8 |
||
integer |
2**8 |
||
integer |
0 |
Ports
Count: 16
Name |
Mode |
Type |
Description |
---|---|---|---|
in |
std_logic |
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in |
std_logic |
||
in |
std_logic_vector ( G_DWIDTH - 1 downto 0 ) |
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in |
std_logic |
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in |
std_logic |
||
out |
std_logic_vector ( G_DWIDTH - 1 downto 0 ) |
||
in |
std_logic |
||
out |
std_logic |
||
in |
std_logic |
||
out |
std_logic |
||
out |
std_logic |
||
out |
std_logic |
||
out |
std_logic |
||
out |
std_logic |
||
out |
std_logic_vector ( G_AWIDTH - 1 downto 0 ) |
||
out |
std_logic_vector ( G_AWIDTH - 1 downto 0 ) |