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# Entity - FIFO_DC
## Summary
| Name | Location | Description |
| --- | --- | --- |
|FIFO_DC|fifo_dc.vhd#36||
## Instantiations
Count: 22
| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| fifo_dc_inst | FIFO_DC_AXIS_S.vhd#183 | | [
](module_3/instantiation_1.md) |
| fifo_dc_inst | FIFO_DC_AXIS_S.vhd#183 | | [](module_3/instantiation_2.md) |
| fifo_dc_inst | FIFO_DC_AXIS_S.vhd#183 | | [](module_3/instantiation_3.md) |
| fifo_dc_inst | FIFO_DC_AXIS_S.vhd#183 | | [](module_3/instantiation_4.md) |
| fifo_dc_inst | FIFO_DC_AXIS_S.vhd#183 | | [](module_3/instantiation_5.md) |
| fifo_dc_inst | FIFO_DC_AXIS_S.vhd#183 | | [](module_3/instantiation_6.md) |
| fifo_dc_inst | FIFO_DC_AXIS_S.vhd#183 | | [](module_3/instantiation_7.md) |
| fifo_dc_inst | FIFO_DC_AXIS_S.vhd#183 | | [](module_3/instantiation_8.md) |
| fifo_dc_inst | FIFO_DC_AXIS_S.vhd#183 | | [](module_3/instantiation_9.md) |
| fifo_dc_inst | FIFO_DC_AXIS_M.vhd#174 | | [](module_3/instantiation_10.md) |
| fifo_dc_inst | FIFO_DC_AXIS_M.vhd#174 | | [](module_3/instantiation_11.md) |
| fifo_dc_inst | FIFO_DC_AXIS_M.vhd#174 | | [](module_3/instantiation_12.md) |
| fifo_dc_inst | FIFO_DC_AXIS_M.vhd#174 | | [](module_3/instantiation_13.md) |
| fifo_dc_inst | FIFO_DC_AXIS_M.vhd#174 | | [](module_3/instantiation_14.md) |
| fifo_dc_inst | FIFO_DC_AXIS_M.vhd#174 | | [](module_3/instantiation_15.md) |
| fifo_dc_inst | FIFO_DC_AXIS_M.vhd#174 | | [](module_3/instantiation_16.md) |
| fifo_dc_inst | FIFO_DC_AXIS_M.vhd#174 | | [](module_3/instantiation_17.md) |
| fifo_dc_inst | FIFO_DC_AXIS_M.vhd#174 | | [](module_3/instantiation_18.md) |
| inst_fifo_in_ctrl | phy_plus_lane.vhd#718 | | [](module_3/instantiation_19.md) |
| inst_fifo_tx_data | phy_plus_lane.vhd#750 | | [](module_3/instantiation_20.md) |
| inst_fifo_rx_data | phy_plus_lane.vhd#922 | | [](module_3/instantiation_21.md) |
| inst_fifo_out_ctrl | phy_plus_lane.vhd#957 | | [](module_3/instantiation_22.md) |
## Generics
Count: 4
| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|G_DWIDTH|integer|8||
|G_AWIDTH|integer|8||
|G_THRESHOLD_HIGH|integer|2**8||
|G_THRESHOLD_LOW|integer|0||
## Ports
Count: 16
| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|RST_N|in|std_logic||
|WR_CLK|in|std_logic||
|WR_DATA|in|std_logic_vector ( G_DWIDTH - 1 downto 0 )||
|WR_DATA_EN|in|std_logic||
|RD_CLK|in|std_logic||
|RD_DATA|out|std_logic_vector ( G_DWIDTH - 1 downto 0 )||
|RD_DATA_EN|in|std_logic||
|RD_DATA_VLD|out|std_logic||
|CMD_FLUSH|in|std_logic||
|STATUS_BUSY_FLUSH|out|std_logic||
|STATUS_THRESHOLD_HIGH|out|std_logic||
|STATUS_THRESHOLD_LOW|out|std_logic||
|STATUS_FULL|out|std_logic||
|STATUS_EMPTY|out|std_logic||
|STATUS_LEVEL_WR|out|std_logic_vector ( G_AWIDTH - 1 downto 0 )||
|STATUS_LEVEL_RD|out|std_logic_vector ( G_AWIDTH - 1 downto 0 )||
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