spacefibrelight

  • Summary Report
  • Design Hierarchy
    • Summary
    • Dependencies
    • VHDL Entities
    • VHDL Packages
  • Clock Domains
    • Clock Domains
    • Clock Management Module (CMM)
  • Reset Domains
    • Global Reset Domains
    • Local Reset Domains
    • Reset Management Module (RMM)
  • Clock Domain Crossings (CDC)
  • Reset Domain Crossings (RDC)
  • Finite State Machines (FSM)
  • Combinational Loops
  • Latches
spacefibrelight

  • Entity - data_link_reset
  • View page source

Entity - data_link_reset

Summary

Name

Location

Description

data_link_reset

data_link_reset.vhd#32

Instantiations

Count: 1

Name

Location

Description

Details

inst_data_link_reset

data_link.vhd#1008

Details

Generics

Count: 1

Name

Type

Default value

Description

G_VC_NUM

integer

8

Number of virtual channels

Ports

Count: 12

Name

Mode

Type

Description

RST_N

in

std_logic

Global reset (Active-low)

CLK

in

std_logic

Global clock

LINK_RESET_DLRE

out

std_logic

Link Reset command

LINK_RESET_DIBUF

in

std_logic_vector ( G_VC_NUM - 1 downto 0 )

Link Reset request from data_in_buf

LINK_RESET_DERRM

in

std_logic

Link Reset request from data_err_management

LANE_RESET_DLRE

out

std_logic

Lane Reset command

NEAR_END_CAPA_DLRE

out

std_logic_vector ( 7 downto 0 )

Near-end capability

LANE_ACTIVE_PPL

in

std_logic

Lane active flag

FAR_END_CAPA_PPL

in

std_logic_vector ( 7 downto 0 )

Far-end capability

RESET_PARAM_DLRE

out

std_logic

Reset all MIB parameters command

INTERFACE_RESET_MIB

in

std_logic

Interface Reset request

LINK_RESET_MIB

in

std_logic

Link Reset request


spacefibrelight

Generated September 24, 2026 at 11:16:52 by Linty