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Entity - ppl_64_skip_insertion

Summary

Name	Location	Description
ppl_64_skip_insertion	ppl_64_skip_insertion.vhd#30

Instantiations

Count: 0

Generics

Count: 0

Ports

Count: 9

Name	Mode	Type	Description
RST_N	in	std_logic	Global reset (Active low)
CLK	in	std_logic	Clock generated by HSSL IP
NEW_DATA_PLCWI	in	std_logic	New data Flag
DATA_TX_PLCWI	in	std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )	Data 64-bit received from DATA_LINK layer
VALID_K_CHARAC_PLCWI	in	std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )	Flags indicate which byte is a K character from DATA-LINK layer
WAIT_SEND_DATA_PLSI	out	std_logic	Flag to indicate that the lane_ctrl_word_insert sends a SKIP control word
DATA_TX_PLSI	out	std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )	Data 64-bit sent to manufacturer IP
VALID_K_CHARAC_PLSI	out	std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )	Flags indicate which byte is a K character
ENABLE_TRANSM_DATA_PLIF	in	std_logic	Flag to enable sending data

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