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Entity - ppl_64_lane_ctrl_word_detect

Summary

Name

Location

Description

ppl_64_lane_ctrl_word_detect

ppl_64_lane_ctrl_word_detect.vhd#32

Instantiations

Count: 0

Generics

Count: 0

Ports

Count: 24

Name

Mode

Type

Description

RST_N

in

std_logic

Global reset. Active Low

CLK

in

std_logic

Clock generated by HSSL IP

NO_SIGNAL_PLCWD

out

std_logic

Flag indicating that no signal is received

RX_NEW_WORD_PLCWD

out

std_logic_vector ( 1 downto 0 )

Flag indicating that a new word has been received

DETECTED_INIT1_PLCWD

out

std_logic_vector ( 1 downto 0 )

Flag indicating INIT1 control word received

DETECTED_INIT2_PLCWD

out

std_logic_vector ( 1 downto 0 )

Flag indicating INIT2 control word received

DETECTED_INIT3_PLCWD

out

std_logic_vector ( 1 downto 0 )

Flag indicating INIT3 control word received

DETECTED_INV_INIT1_PLCWD

out

std_logic_vector ( 1 downto 0 )

Flag indicating INV_INIT1 control word received

DETECTED_INV_INIT2_PLCWD

out

std_logic_vector ( 1 downto 0 )

Flag indicating INV_INIT2 control word received

DETECTED_RXERR_WORD_PLCWD

out

std_logic_vector ( 1 downto 0 )

Flag indicating RXERR control word detected

DETECTED_LOSS_SIGNAL_PLCWD

out

std_logic_vector ( 1 downto 0 )

Flag indicating LOSS_SIGNAL control word detected

DETECTED_STANDBY_PLCWD

out

std_logic_vector ( 1 downto 0 )

Flag indicating STANDBY control word detected

COMMA_K287_RXED_PLCWD

out

std_logic_vector ( 1 downto 0 )

Comma K28.7 character received flag

CAPABILITY_PLCWD

out

std_logic_vector ( 7 downto 0 )

Capability extracted from INIT3 control word: bits [31:24] and [63:56]

SEND_RXERR_PLIF

in

std_logic_vector ( 1 downto 0 )

Flag to send RXERR control word to Data-Link layer when FSM exits ACTIVE_ST

NO_SIGNAL_DETECTION_ENABLED_PLIF

in

std_logic

Flag to enable the no-signal detection function

ENABLE_TRANSM_DATA_PLIF

in

std_logic

Flag to enable the transmission of data

DATA_RX_PLPL

in

std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )

64-bit data from ppl_64_parallel_loopback

VALID_K_CHARAC_PLPL

in

std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )

8-bit valid K character flags from ppl_64_parallel_loopback

DATA_RDY_PLPL

in

std_logic

Data valid flag from ppl_64_parallel_loopback

LOSS_OF_SIGNAL_PLPL

in

std_logic

Loss of signal flag from ppl_64_parallel_loopback

DATA_RX_PLCWD

out

std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )

64-bit data sent to Data-Link layer

VALID_K_CHARAC_PLCWD

out

std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )

8-bit valid K character flags sent to Data-Link layer

DATA_RDY_PLCWD

out

std_logic_vector ( 1 downto 0 )

Data valid flag sent to Data-Link layer


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