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Entity - ppl_64_rx_wr_en_fifo

Summary

Name	Location	Description
ppl_64_rx_wr_en_fifo	ppl_64_rx_wr_en_fifo.vhd#32

Instantiations

Count: 0

Generics

Count: 0

Ports

Count: 9

Name	Mode	Type	Description
RST_N	in	std_logic	Global reset. Active Low
CLK	in	std_logic	Clock generated by HSSL IP
DATA_RX_PLCWD	in	std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )	64-bit data from ppl_64_lane_ctrl_word_detect
VALID_K_CHARAC_PLCWD	in	std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )	8-bit valid K character flags from ppl_64_lane_ctrl_word_detect
DATA_RDY_PLCWD	in	std_logic_vector ( 1 downto 0 )	Data valid flag from ppl_64_lane_ctrl_word_detect
DATA_RX_PLRWEF	out	std_logic_vector ( C_DATA_WIDTH - 1 downto 0 )	64-bit data to fifo_rx_data
VALID_K_CHARAC_PLRWEF	out	std_logic_vector ( C_K_CHAR_WIDTH - 1 downto 0 )	8-bit valid K character flags to fifo_rx_data
DATA_RDY_PLRWEF	out	std_logic_vector ( 1 downto 0 )	Data valid flag to fifo_rx_data
DATA_WR_EN_PLRWEF	out	std_logic	Write enable flag to fifo_rx_data

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