spacefibrelight

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  • Design Hierarchy
    • Summary
    • Dependencies
    • VHDL Entities
    • VHDL Packages
  • Clock Domains
    • Clock Domains
    • Clock Management Module (CMM)
  • Reset Domains
    • Global Reset Domains
    • Local Reset Domains
    • Reset Management Module (RMM)
  • Clock Domain Crossings (CDC)
  • Reset Domain Crossings (RDC)
  • Finite State Machines (FSM)
  • Combinational Loops
  • Latches
spacefibrelight

  • Package - data_link_lib
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Package - data_link_lib

Summary

Name

Location

Description

data_link_lib

pkg_data_link.vhd#32

Constants

Count: 53

Name

Type

Default value

Description

C_CAPA_LINK_RST

integer

0

Link Reset bitfield in lane capability vector

C_CAPA_LANE_START

integer

1

Lane Start bitfield in lane capability vector

C_CAPA_DATA_SCRAM

integer

2

Data Scrambled bitfield in lane capability vector

C_CAPA_MULTI_LANE

integer

3

Multi-Lane bitfield in lane capability vector

C_CAPA_ROUTING_SW

integer

4

Routing Switch bitfield in lane capability vector

C_OUT_BUF_SIZE

integer

7

fifo depth = 2**7= 128 words of 32 bits

C_FCT_CC_SIZE

integer

8

FCT credit counter size: 4x64xM = 256

C_FCT_CC_MAX

unsigned

to_unsigned ( 255 , C_FCT_CC_SIZE )

FCT credit counter size: 4x64xM = 256

C_M_SIZE

integer

4

Size of M which is multiplier +1

C_MULT_SIZE

integer

3

Size of multiplier

C_CHANNEL_SIZE

integer

5

Channel number field

C_MID_BUF_SIZE

integer

7

fifo depth = 2**7= 128 words of 32 bits for the middle buffer (data)

C_MID_BUF_BC_SIZE

integer

3

fifo depth = 2**3= 8 words of 32 bits for the middle buffer (broadcast)

C_IN_BUF_SIZE

integer

8

fifo depth = 2**8= 256 words of 32 bits for the input buffer

C_DATA_LENGTH

integer

32

Data width

C_BYTE_BY_WORD_LENGTH

integer

4

Number of byte in a word

C_DATA_K_WIDTH

integer

C_DATA_LENGTH + C_BYTE_BY_WORD_LENGTH

Data + k character width

C_TYPE_FRAME_LENGTH

integer

4

Type of frame vector width

C_MAX_DATA_FRAME

unsigned ( 7 downto 0 )

to_unsigned ( 65 , 8 )

Maximum number of words in a Data frame

C_MAX_IDLE_FRAME

unsigned ( 7 downto 0 )

to_unsigned ( 64 , 8 )

Maximum number of words in an Idle frame

C_WORD_BC_FRAME

unsigned ( 1 downto 0 )

to_unsigned ( 2 , 2 )

Number of words in a Broadcast frame

C_BYTE_WIDTH

integer

8

Byte width

C_DATA_FRM

std_logic_vector ( 3 downto 0 )

“0001”

DATA Frame

C_BC_FRM

std_logic_vector ( 3 downto 0 )

“0010”

BROADCAST Frame

C_IDLE_FRM

std_logic_vector ( 3 downto 0 )

“0011”

IDLE Frame

C_FCT_FRM

std_logic_vector ( 3 downto 0 )

“0100”

FCT Frame

C_ACK_FRM

std_logic_vector ( 3 downto 0 )

“0101”

ACK Frame

C_NACK_FRM

std_logic_vector ( 3 downto 0 )

“0110”

NACK Frame

C_FULL_FRM

std_logic_vector ( 3 downto 0 )

“0111”

FULL Frame

C_RETRY_FRM

std_logic_vector ( 3 downto 0 )

“1000”

RETRY Frame

C_EEP_SYMB

std_logic_vector ( 07 downto 00 )

x”FE”

K30.7 EEP

C_EOP_SYMB

std_logic_vector ( 07 downto 00 )

x”FD”

K29.7 EOP

C_K28_7_SYMB

std_logic_vector ( 07 downto 00 )

x”FC”

K28.7 Comma

C_K28_3_SYMB

std_logic_vector ( 07 downto 00 )

x”7C”

K28.3 FCT

C_K28_2_SYMB

std_logic_vector ( 07 downto 00 )

x”5C”

K28.2 EBF

C_K28_0_SYMB

std_logic_vector ( 07 downto 00 )

x”1C”

K28.0 EDF

C_FILL_SYMB

std_logic_vector ( 07 downto 00 )

x”FB”

K27.7

C_SBF_SYMB

std_logic_vector ( 07 downto 00 )

x”5D”

D29.2 SBF

C_NACK_SYMB

std_logic_vector ( 07 downto 00 )

x”BB”

D27.5

C_SDF_SYMB

std_logic_vector ( 07 downto 00 )

x”50”

D16.2

C_FULL_SYMB

std_logic_vector ( 07 downto 00 )

x”6F”

D15.3

C_RETRY_SYMB

std_logic_vector ( 07 downto 00 )

x”87”

D7.4

C_SIF_SYMB

std_logic_vector ( 07 downto 00 )

x”84”

D4.2 SIF

C_ACK_SYMB

std_logic_vector ( 07 downto 00 )

x”A2”

D2.5

C_RESERVED_SYMB

std_logic_vector ( 07 downto 00 )

x”00”

D0.0

C_SDF_WORD

std_logic_vector ( 15 downto 00 )

C_SDF_SYMB & C_K28_7_SYMB

2 first bytes of a Start of Data Frame word

C_SBF_WORD

std_logic_vector ( 15 downto 00 )

C_SBF_SYMB & C_K28_7_SYMB

2 first bytes of a Start of Broadcast Frame word

C_SIF_WORD

std_logic_vector ( 15 downto 00 )

C_SIF_SYMB & C_K28_7_SYMB

2 first bytes of a Start of Idle Frame word

C_ACK_WORD

std_logic_vector ( 15 downto 00 )

C_ACK_SYMB & C_K28_7_SYMB

2 first bytes of a ACK word

C_NACK_WORD

std_logic_vector ( 15 downto 00 )

C_NACK_SYMB & C_K28_7_SYMB

2 first bytes of a NACK word

C_FULL_WORD

std_logic_vector ( 15 downto 00 )

C_FULL_SYMB & C_K28_7_SYMB

2 first bytes of a FULL word

C_RETRY_WORD

std_logic_vector

C_RESERVED_SYMB & C_RESERVED_SYMB & C_RETRY_SYMB & C_K28_7_SYMB

Retry word

C_RXERR_WORD

std_logic_vector

C_RESERVED_SYMB & C_RESERVED_SYMB & C_RESERVED_SYMB & C_RESERVED_SYMB

RXERR word

Types

Count: 5

Name

Definition

Description

int_array

array ( natural range <> ) of integer

vc_data_array

array ( natural range <> ) of std_logic_vector ( C_DATA_LENGTH - 1 downto 0 )

vc_k_array

array ( natural range <> ) of std_logic_vector ( C_BYTE_BY_WORD_LENGTH - 1 downto 0 )

vc_data_k_array

array ( natural range <> ) of std_logic_vector ( C_DATA_LENGTH + C_BYTE_BY_WORD_LENGTH - 1 downto 0 )

vc_m_val_array

array ( natural range <> ) of std_logic_vector ( C_M_SIZE - 1 downto 0 )

Subtypes

Count: 0

Functions

Count: 3

Name

Returned type

Description

Details

calculate_crc_16

STD_LOGIC_VECTOR

Calcluates the crc 16 bits

Details

calculate_crc_8

STD_LOGIC_VECTOR

Calcluates the crc 8 bits

Details

calculate_idle

STD_LOGIC_VECTOR

Calcluates Idle data

Details

Procedures

Count: 0

Global Signals

Count: 0

Global Variables

Count: 0

Component Definitions

Count: 0


spacefibrelight

Generated September 24, 2026 at 11:16:52 by Linty