gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising) => CLK (rising)

Graph

Number of RDCs

30

ID

Graph

Reset (source)

Flip-flop (destination)

6

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#208

19

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#222

40

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#256

104

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#179

114

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#199

116

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#135

117

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#135

118

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#135

119

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#135

135

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#256

144

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#256

152

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440

153

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#199

154

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440

155

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440

162

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440

163

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440

165

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#440

167

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#102

175

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#102

177

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#102

178

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#102

179

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#102

199

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#440

222

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#240

248

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#199

252

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#199

254

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: gen_inst_phy_plus_lane.inst_phy_plus_lane.reset_n
  - LANE_RESET: spacefibre_light_top.vhd#139 (Port)
  - RST_N: spacefibre_light_top.vhd#50 (Port)
  - gen_inst_phy_plus_lane.inst_phy_plus_lane.lane_reset_dl_i: phy_plus_lane_64b.vhd#722 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_ppl_64_init_hssl (ppl_64_init_hssl) > ppl_64_init_hssl.vhd#179

257

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_tx_data (FIFO_DC) > fifo_dc.vhd#240

273

Graph

Clock domain: gen_inst_phy_plus_lane.inst_phy_plus_lane.clk_tx (rising)

Reset: inst_reset_sync_clk_from_GTY.reset_gen_rr_n: reset_gen.vhd#56 (Flip-flop)

Clock domain: CLK (rising)

Flip-flop: TOP (spacefibre_light_top) > gen_inst_phy_plus_lane.inst_phy_plus_lane (phy_plus_lane_64b) > inst_fifo_in_ctrl (FIFO_DC) > fifo_dc.vhd#222