10 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
12 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
13 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
14 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
15 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
16 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
17 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
20 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
21 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
22 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
23 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
24 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
25 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
26 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
27 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
28 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
29 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
30 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
31 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
32 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
34 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
35 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
36 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
37 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
38 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
39 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
41 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
48 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
49 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
50 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
51 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
52 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
53 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
54 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
55 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
56 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
57 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
58 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
59 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
60 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
61 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
62 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(1).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(1).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
73 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
74 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
75 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
76 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
77 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
78 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
79 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
83 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
85 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
86 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
87 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
88 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
89 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
90 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
91 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(2).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(2).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
97 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
98 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
99 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
100 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
101 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
102 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
103 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
107 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
108 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
109 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
110 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
111 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
112 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
113 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
121 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
122 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
123 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
124 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
125 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
126 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
127 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
128 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
129 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
130 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
131 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
132 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
133 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
134 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
137 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
138 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
139 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
140 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
141 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
142 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
143 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
145 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
146 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
147 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
148 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
149 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
150 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
151 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
166 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
169 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
170 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
171 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
172 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
173 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
174 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
180 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
181 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
182 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
183 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
184 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
185 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
186 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
193 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
194 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
195 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
196 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
197 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
198 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
200 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
201 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
202 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
203 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
204 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
205 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
225 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
226 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > AXIS_SLAVE_inst (AXIS_SLAVE) > AXIS_SLAVE.vhd#56 |
238 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.inst_data_out_bc_buf.rst_n_fifo: data_out_bc_buf.vhd#172 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_out_bc_buf (data_out_bc_buf) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
249 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(0).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(0).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
255 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(3).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(3).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
256 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(4).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(4).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
258 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(5).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(5).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
260 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(6).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(6).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
266 |
Graph |
Clock domain: CLK (rising)
Reset: inst_data_link.gen_data_out_buff(7).inst_data_out_buff.rst_n_fifo: data_out_buf.vhd#225 (Flip-flop) |
Clock domain: AXIS_ACLK_TX_DL (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_out_buff(7).inst_data_out_buff (data_out_buff) > ints_fifo_dc_axis_s (FIFO_DC_AXIS_S) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |