1 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
2 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
3 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
4 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
5 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
7 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
8 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
9 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
11 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
18 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
33 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
42 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
43 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
44 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
45 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
46 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
47 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
63 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
64 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
65 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
66 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
67 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
68 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
69 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
70 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
71 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
72 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
80 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
81 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
82 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
84 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
92 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
93 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
94 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
95 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
96 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
105 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
106 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
115 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
120 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
136 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
156 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
157 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
158 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
159 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
160 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
161 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
164 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
168 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
176 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
187 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
188 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
189 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
190 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
191 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
192 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
206 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
207 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
208 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
209 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
210 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
211 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
212 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
213 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
214 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
215 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
216 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
217 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
218 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
219 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
220 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(5).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(5).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
221 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(7).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(7).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
223 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
224 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
227 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
228 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
229 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
230 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
231 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
232 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
233 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
234 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(6).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(6).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
235 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
236 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
237 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
239 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#199 |
240 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
241 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
242 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
243 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
244 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
245 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
246 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
247 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
250 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
251 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#256 |
253 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.inst_data_in_bc_buf.rst_n_fifo: data_in_bc_buf.vhd#158 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > inst_data_in_bc_buf (data_in_bc_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
259 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
261 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
262 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
263 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(3).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(3).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
264 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(0).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(0).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
265 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
267 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
268 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
269 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
270 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
271 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(4).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(4).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |
272 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#240 |
274 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
275 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
276 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
277 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
278 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
279 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(1).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(1).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#440 |
280 |
Graph |
Clock domain: AXIS_ACLK_RX_DL (rising)
Reset: inst_data_link.gen_data_in_buff(2).inst_data_in_buf.rst_n_fifo: data_in_buf.vhd#194 (Flip-flop) |
Clock domain: CLK (rising)
Flip-flop: TOP (spacefibre_light_top) > inst_data_link (data_link) > gen_data_in_buff(2).inst_data_in_buf (data_in_buf) > ints_fifo_dc_axis_m (FIFO_DC_AXIS_M) > fifo_dc_inst (FIFO_DC) > fifo_dc.vhd#222 |