spacefibrelight
Summary Report
Design Hierarchy
Summary
Dependencies
VHDL Entities
VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Finite State Machines (FSM)
Combinational Loops
Latches
spacefibrelight
Procedure - log_test_result
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Procedure - log_test_result
Summary
Name
Description
log_test_result
Parameters
Count: 1
Name
Mode
Type
Description
test_failed
boolean