spacefibrelight
Summary Report
Design Hierarchy
Summary
Dependencies
VHDL Entities
VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Finite State Machines (FSM)
Combinational Loops
Latches
spacefibrelight
Function - or_all
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Function - or_all
Summary
Name
Returned type
Description
or_all
std_logic
Parameters
Count: 1
Name
Mode
Type
Description
A
std_logic_vector