spacefibrelight
Summary Report
Design Hierarchy
Summary
Dependencies
VHDL Entities
VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Finite State Machines (FSM)
Combinational Loops
Latches
spacefibrelight
Instantiation - inst_reset_sync_clk_from_GTY
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Instantiation - inst_reset_sync_clk_from_GTY
Summary
Name
Architecture
Description
inst_reset_sync_clk_from_GTY
rtl
Generics
Count: 0