spacefibrelight
Summary Report
Design Hierarchy
Summary
Dependencies
VHDL Entities
VHDL Packages
Clock Domains
Clock Domains
Clock Management Module (CMM)
Reset Domains
Global Reset Domains
Local Reset Domains
Reset Management Module (RMM)
Clock Domain Crossings (CDC)
Reset Domain Crossings (RDC)
Finite State Machines (FSM)
Combinational Loops
Latches
spacefibrelight
Instantiation - gen_data_in_buff(6).inst_data_in_buf
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Instantiation - gen_data_in_buff(6).inst_data_in_buf
Summary
Name
Architecture
Description
gen_data_in_buff(6).inst_data_in_buf
rtl
Generics
Count: 0