# Summary Report

|Report|Summary|Details|
|---|---|:---:|
|**Design Hierarchy**|Modules: 35<br>Instantiations: 103|[<img title="View Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Details">](design_hierarchy.md)|
|**Clock Domains**|Clock domains: 4|[<img title="View Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Details">](clock_domains.md)|
|**Reset Domains**|Global reset domains: 7|[<img title="View Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Details">](reset_domains.md)|
|**Clock Domain Crossings (CDC)**|CDCs: 322|[<img title="View Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Details">](clock_domain_crossings.md)|
|**Reset Domain Crossings (RDC)**|RDCs: 268|[<img title="View Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Details">](reset_domain_crossings.md)|
|**Finite State Machines (FSM)**|FSMs: 10|[<img title="View Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Details">](finite_state_machines.md)|
|**Combinational Loops**|Loops: 0|[<img title="View Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Details">](combinational_loops.md)|