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# FSM #6: current_state_req ## Summary |Name|Location|Graph|Reset State|States|Input Signals|Output Signals| |---|---|:---:|---|---|---:|---:| current_state_req|data_mac.vhd#96|Open FSM Diagram|IDLE_ST| Count: 2
END_ST
IDLE_ST
REQ_ST
START_ENCAPS_ST
TRANSFER_ST|13|1||
## Input Signals Count: 13 |Name|Declaration| |---|---| |LANE_ACTIVE_PPL|data_mac.vhd#41| |LINK_RESET_DLRE|data_mac.vhd#39| |REQ_ACK_DERRM|data_mac.vhd#43| |REQ_FCT_DIBUF|data_mac.vhd#49| |REQ_NACK_DERRM|data_mac.vhd#44| |TYPE_FRAME_DMAC|data_mac.vhd#71| |VC_DATA_VALID_DOBUF|data_mac.vhd#55| |VC_END_PACKET_DOBUF|data_mac.vhd#56| |cnt_wait|data_mac.vhd#109| |cnt_wait_ack|data_mac.vhd#108| |current_channel|data_mac.vhd#111| |current_state_vc|data_mac.vhd#95| |type_frame|data_mac.vhd#98|| ## Output Signals Count: 1 |Name|Declaration| |---|---| |current_state_vc|data_mac.vhd#95| ## Transition table |From|To|Input Control Signals| |---|---|---| |IDLE_ST|IDLE_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39| |IDLE_ST|IDLE_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
REQ_ACK_DERRM: data_mac.vhd#43
REQ_FCT_DIBUF: data_mac.vhd#49
REQ_NACK_DERRM: data_mac.vhd#44
TYPE_FRAME_DMAC: data_mac.vhd#71
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
cnt_wait: data_mac.vhd#109
cnt_wait_ack: data_mac.vhd#108
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95
type_frame: data_mac.vhd#98| |IDLE_ST|IDLE_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |IDLE_ST|IDLE_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |IDLE_ST|IDLE_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |IDLE_ST|IDLE_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |IDLE_ST|IDLE_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
current_state_vc: data_mac.vhd#95| |IDLE_ST|IDLE_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
current_state_vc: data_mac.vhd#95| |IDLE_ST|IDLE_ST|LINK_RESET_DLRE: data_mac.vhd#39| |IDLE_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
REQ_ACK_DERRM: data_mac.vhd#43
REQ_FCT_DIBUF: data_mac.vhd#49
REQ_NACK_DERRM: data_mac.vhd#44
TYPE_FRAME_DMAC: data_mac.vhd#71
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
cnt_wait: data_mac.vhd#109
cnt_wait_ack: data_mac.vhd#108
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95
type_frame: data_mac.vhd#98| |IDLE_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |TRANSFER_ST|IDLE_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
current_state_vc: data_mac.vhd#95| |TRANSFER_ST|IDLE_ST|LINK_RESET_DLRE: data_mac.vhd#39| |TRANSFER_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39| |TRANSFER_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
REQ_ACK_DERRM: data_mac.vhd#43
REQ_FCT_DIBUF: data_mac.vhd#49
REQ_NACK_DERRM: data_mac.vhd#44
TYPE_FRAME_DMAC: data_mac.vhd#71
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
cnt_wait: data_mac.vhd#109
cnt_wait_ack: data_mac.vhd#108
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95
type_frame: data_mac.vhd#98| |TRANSFER_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
REQ_ACK_DERRM: data_mac.vhd#43
REQ_FCT_DIBUF: data_mac.vhd#49
REQ_NACK_DERRM: data_mac.vhd#44
TYPE_FRAME_DMAC: data_mac.vhd#71
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
cnt_wait: data_mac.vhd#109
cnt_wait_ack: data_mac.vhd#108
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95
type_frame: data_mac.vhd#98| |TRANSFER_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |TRANSFER_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |TRANSFER_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |TRANSFER_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
VC_END_PACKET_DOBUF: data_mac.vhd#56
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |TRANSFER_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
VC_DATA_VALID_DOBUF: data_mac.vhd#55
current_channel: data_mac.vhd#111
current_state_vc: data_mac.vhd#95| |TRANSFER_ST|TRANSFER_ST|LANE_ACTIVE_PPL: data_mac.vhd#41
LINK_RESET_DLRE: data_mac.vhd#39
current_state_vc: data_mac.vhd#95|
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