[Back to Design Hierarchy Report](../design_hierarchy.md#vhdl-packages)
# Package - pkg_phy_plus_lane_64b
## Summary
| Name | Location | Description |
| --- | --- | --- |
|pkg_phy_plus_lane_64b|pkg_phy_plus_lane_64b.vhd#34||
## Constants
Count: 38
| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|C_DATA_WIDTH|integer|64|Data width|
|C_K_CHAR_WIDTH|integer|8|K character width|
|C_K28_5_SYMB|std_logic_vector ( 07 downto 00 )|x"BC"|K28.5|
|C_K28_7_SYMB|std_logic_vector ( 07 downto 00 )|x"FC"|K28.7|
|C_LOST_SIG_SYMB|std_logic_vector ( 07 downto 00 )|x"64"|D04.3|
|C_INIT1_SYMB|std_logic_vector ( 07 downto 00 )|x"46"|D06.2|
|C_I_INIT1_SYMB|std_logic_vector ( 07 downto 00 )|x"B9"|D25.5|
|C_INIT2_SYMB|std_logic_vector ( 07 downto 00 )|x"A6"|D06.5|
|C_I_INIT2_SYMB|std_logic_vector ( 07 downto 00 )|x"59"|D25.2|
|C_INIT3_SYMB|std_logic_vector ( 07 downto 00 )|x"38"|D24.1|
|C_LLCW_SYMB|std_logic_vector ( 07 downto 00 )|x"CE"|D14.6|
|C_I_LLCW_SYMB|std_logic_vector ( 07 downto 00 )|x"31"|D17.1|
|C_STANDBY_SYMB|std_logic_vector ( 07 downto 00 )|x"7E"|D30.3|
|C_SKIP_SYMB|std_logic_vector ( 07 downto 00 )|x"7F"|D31.3|
|C_IDLE_SYMB|std_logic_vector ( 07 downto 00 )|x"CF"|D15.6|
|C_RXERR_SYMB|std_logic_vector ( 07 downto 00 )|x"00"|K00.0 and D00.0|
|C_SKIP_WORD|std_logic_vector ( 31 downto 00 )|C_SKIP_SYMB & C_SKIP_SYMB & C_LLCW_SYMB & C_K28_7_SYMB||
|C_IDLE_WORD|std_logic_vector ( 31 downto 00 )|C_IDLE_SYMB & C_IDLE_SYMB & C_LLCW_SYMB & C_K28_7_SYMB||
|C_INIT1_WORD|std_logic_vector ( 31 downto 00 )|C_INIT1_SYMB & C_INIT1_SYMB & C_LLCW_SYMB & C_K28_5_SYMB||
|C_INIT2_WORD|std_logic_vector ( 31 downto 00 )|C_INIT2_SYMB & C_INIT2_SYMB & C_LLCW_SYMB & C_K28_5_SYMB||
|C_INIT3_WORD|std_logic_vector ( 23 downto 00 )|C_INIT3_SYMB & C_LLCW_SYMB & C_K28_5_SYMB|bits 31 downto 24 = Capability field|
|C_I_INIT1_WORD|std_logic_vector ( 31 downto 00 )|C_I_INIT1_SYMB & C_I_INIT1_SYMB & C_I_LLCW_SYMB & C_K28_5_SYMB||
|C_I_INIT2_WORD|std_logic_vector ( 31 downto 00 )|C_I_INIT2_SYMB & C_I_INIT2_SYMB & C_I_LLCW_SYMB & C_K28_5_SYMB||
|C_STANDBY_WORD|std_logic_vector ( 23 downto 00 )|C_STANDBY_SYMB & C_LLCW_SYMB & C_K28_7_SYMB|bits 31 downto 24 = Reason field|
|C_LOST_SIG_WORD|std_logic_vector ( 23 downto 00 )|C_LOST_SIG_SYMB & C_LLCW_SYMB & C_K28_7_SYMB|bits 31 downto 24 = Reason field|
|C_RXERR_WORD|std_logic_vector ( 31 downto 00 )|C_RXERR_SYMB & C_RXERR_SYMB & C_RXERR_SYMB & C_RXERR_SYMB||
|C_PRBS_COUNTER_64|unsigned ( 31 downto 00 )|to_unsigned ( 66 , 32 )|66 = 2 to 65 values. Max value of PRBS counter for INIT1/2/3 control words|
|C_X32_SIGNAL|unsigned ( 04 downto 00 )|"11111"|32 = 0 to 31 values|
|C_5000_WORDS|unsigned ( 12 downto 00 )|to_unsigned ( 4998 , 13 )|4999 = 0 to 4998 values|
|C_SYMB_X5|unsigned ( 02 downto 00 )|"100"|5 = 0 to 4 values|
|C_RDY_WORD|integer|2|2 words by data bus|
|C_DWIDTH|integer|C_DATA_WIDTH + C_K_CHAR_WIDTH|data + k character|
|C_AWIDTH_TX|integer|5|2^5 x 72 = 288 B|
|C_AWIDTH_RX|integer|12|2^12 x 72 = 36 kB|
|C_DWIDTH_CTRL_TX|integer|9|CAPABILITY_TX + LANE_RESET_DL|
|C_AWIDTH_CTRL_TX|integer|3|2^3 x 9 = 9 B|
|C_DWIDTH_CTRL_RX|integer|9|FAR_END_CAPA + LANE_ACTIVE|
|C_AWIDTH_CTRL_RX|integer|3|2^3 x 9 = 9 B|
## Types
Count: 0
## Subtypes
Count: 0
## Functions
Count: 0
## Procedures
Count: 0
## Global Signals
Count: 0
## Global Variables
Count: 0
## Component Definitions
Count: 0
[Back to Design Hierarchy Report](../design_hierarchy.md#vhdl-packages)