[Back to Design Hierarchy Report](../design_hierarchy.md#vhdl-packages)
# Package - PKG_TOOLS
## Summary
| Name | Location | Description |
| --- | --- | --- |
|PKG_TOOLS|pkg_tools.vhd#47||
## Constants
Count: 0
## Types
Count: 0
## Subtypes
Count: 0
## Functions
Count: 15
| Name | Returned type | Description | Details |
| --- | --- | --- | :---: |
|log2|integer||[
](package_1/function_1.md)|
|or_all|std_logic||[
](package_1/function_2.md)|
|and_all|std_logic||[
](package_1/function_3.md)|
|nand_all|std_logic||[
](package_1/function_4.md)|
|sat|std_logic_vector||[
](package_1/function_5.md)|
|sat|std_logic_vector||[
](package_1/function_6.md)|
|arrondi|std_logic_vector||[
](package_1/function_7.md)|
|arrondi|std_logic_vector||[
](package_1/function_8.md)|
|arrondi|std_logic_vector||[
](package_1/function_9.md)|
|arrondi|std_logic_vector||[
](package_1/function_10.md)|
|arrondi_inf|std_logic_vector||[
](package_1/function_11.md)|
|arrondi_inf|std_logic_vector||[
](package_1/function_12.md)|
|arrondi_sup|std_logic_vector||[
](package_1/function_13.md)|
|absolu|unsigned||[
](package_1/function_14.md)|
|absolu|signed||[
](package_1/function_15.md)|
## Procedures
Count: 2
| Name | Description | Details |
| --- | --- | :---: |
|sat||[
](package_1/procedure_1.md)|
|sat||[
](package_1/procedure_2.md)|
## Global Signals
Count: 0
## Global Variables
Count: 0
## Component Definitions
Count: 0
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