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# Entity - FIFO_DC_DROP_BAD_FRAME
## Summary
| Name | Location | Description |
| --- | --- | --- |
|FIFO_DC_DROP_BAD_FRAME|fifo_dc_drop_bad_frame.vhd#36||
## Instantiations
Count: 2
| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| inst_mid_buf_bc | data_link.vhd#776 | | [
](module_6/instantiation_1.md) |
| inst_mid_buf | data_link.vhd#837 | | [](module_6/instantiation_2.md) |
## Generics
Count: 4
| Name | Type | Default value | Description |
| --- | --- | --- | --- |
|G_DWIDTH|integer|8|Data bus fifo length|
|G_AWIDTH|integer|8|Address bus fifo length|
|G_THRESHOLD_HIGH|integer|2**8|high threshold|
|G_THRESHOLD_LOW|integer|0|low threshold|
## Ports
Count: 18
| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|RST_N|in|std_logic||
|WR_CLK|in|std_logic|Clock|
|WR_DATA|in|std_logic_vector ( G_DWIDTH - 1 downto 0 )|Data write bus|
|WR_DATA_EN|in|std_logic|Write command|
|FRAME_ERROR|in|std_logic|Valid received data|
|END_FRAME|in|std_logic|End of frame|
|RD_CLK|in|std_logic|Clock|
|RD_DATA|out|std_logic_vector ( G_DWIDTH - 1 downto 0 )|Data read bus|
|RD_DATA_EN|in|std_logic|Read command|
|RD_DATA_VLD|out|std_logic|Data valid|
|CMD_FLUSH|in|std_logic|fifo flush|
|STATUS_BUSY_FLUSH|out|std_logic|fifo is flushing|
|STATUS_THRESHOLD_HIGH|out|std_logic|threshold high reached flag (on WR_CLK)|
|STATUS_THRESHOLD_LOW|out|std_logic|threshold low reached flag (on RD_CLK)|
|STATUS_FULL|out|std_logic|full fifo flag (on WR_CLK)|
|STATUS_EMPTY|out|std_logic|empty fifo flag (on RD_CLK)|
|STATUS_LEVEL_WR|out|std_logic_vector ( G_AWIDTH - 1 downto 0 )|FIFO fill level (on WR_CLK)|
|STATUS_LEVEL_RD|out|std_logic_vector ( G_AWIDTH - 1 downto 0 )|FIFO fill level (on RD_CLK)|
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