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# Entity - phy_plus_lane

## Summary

| Name | Location | Description |
| --- | --- | --- |
|phy_plus_lane|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#41">phy_plus_lane.vhd#41</linty-anchor>||
## Instantiations

Count: 1

| Name | Location | Description | Details |
| --- | --- | --- | :---: |
| inst_phy_plus_lane | <linty-anchor href="/src/ip_spacefibre_light_top/spacefibre_light_top.vhd#802">spacefibre_light_top.vhd#802</linty-anchor> |  | [<img title="View Instantiation Details" src="/spacefibrelight/_static/images/icon_details.png" style="max-height: 25px; width: auto;" alt="View Instantiation Details">](module_32/instantiation_1.md) |


## Generics

Count: 0

## Ports

Count: 37

| Name | Mode | Type | Description |
| --- | --- | --- | --- |
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#43">RST_N</linty-anchor>|in|std_logic|global reset|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#44">CLK</linty-anchor>|in|std_logic|Main clock|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#46">LANE_RESET_PPL_OUT</linty-anchor>|out|std_logic||
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#47">RST_TXCLK_N</linty-anchor>|in|std_logic|Synchronous reset on clock generated by GTY PLL|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#48">CLK_TX_OUT</linty-anchor>|out|std_logic|Clock generated by manufacturer IP|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#49">RST_TX_DONE</linty-anchor>|out|std_logic|Up when internal rx reset done|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#51">CLK_GTY</linty-anchor>|in|std_logic|Clock for the extended phy layer IP|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#53">DATA_TX</linty-anchor>|in|std_logic_vector ( 31 downto 00 )|32-bit Data parallel to be send from Data-Link Layer|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#54">LANE_RESET_DL</linty-anchor>|in|std_logic|Lane reset command from Data-Link Layer|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#55">CAPABILITY_TX</linty-anchor>|in|std_logic_vector ( 07 downto 00 )|Capability field send in INIT3 control word|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#56">NEW_DATA_TX</linty-anchor>|in|std_logic|Flag new data|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#57">VALID_K_CHARAC_TX</linty-anchor>|in|std_logic_vector ( 03 downto 00 )|4-bit valid K character flags from Data-link layer|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#58">FIFO_TX_FULL</linty-anchor>|out|std_logic|FiFo TX full flag|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#61">FIFO_RX_RD_EN</linty-anchor>|in|std_logic|FiFo RX read enable flag|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#62">DATA_RX</linty-anchor>|out|std_logic_vector ( 31 downto 00 )|32-bit Data parallel to be received to Data-Link Layer|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#63">FIFO_RX_EMPTY</linty-anchor>|out|std_logic|FiFo RX empty flag|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#64">FIFO_RX_DATA_VALID</linty-anchor>|out|std_logic|FiFo RX data valid flag|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#65">VALID_K_CHARAC_RX</linty-anchor>|out|std_logic_vector ( 03 downto 00 )|4-bit valid K character flags to Data-link layer|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#66">FAR_END_CAPA_DL</linty-anchor>|out|std_logic_vector ( 07 downto 00 )|Capability field receive in INIT3 control word|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#67">LANE_ACTIVE_DL</linty-anchor>|out|std_logic|Lane Active flag for the DATA Link Layer|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#70">TX_POS</linty-anchor>|out|std_logic|Positive LVDS serial data send|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#71">TX_NEG</linty-anchor>|out|std_logic|Negative LVDS serial data send|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#72">RX_POS</linty-anchor>|in|std_logic|Positive LVDS serial data received|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#73">RX_NEG</linty-anchor>|in|std_logic|Negative LVDS serial data received|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#76">LANE_START</linty-anchor>|in|std_logic|Asserts or de-asserts LaneStart for the lane|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#77">AUTOSTART</linty-anchor>|in|std_logic|Asserts or de-asserts AutoStart for the lane|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#78">LANE_RESET</linty-anchor>|in|std_logic|Asserts or de-asserts LaneReset for the lane|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#79">PARALLEL_LOOPBACK_EN</linty-anchor>|in|std_logic|Enables or disables the parallel loopback for the lane|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#80">STANDBY_REASON</linty-anchor>|in|std_logic_vector ( 07 downto 00 )|In case of error, pauses communication|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#81">NEAR_END_SERIAL_LB_EN</linty-anchor>|in|std_logic|Enables or disables the near-end serial loopback for the lane|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#82">FAR_END_SERIAL_LB_EN</linty-anchor>|in|std_logic|Enables or disables the far-end serial loopback for the lane|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#84">LANE_STATE</linty-anchor>|out|std_logic_vector ( 03 downto 00 )|Indicates the current state of the Lane Initialization state machine in a lane|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#85">RX_ERROR_CNT</linty-anchor>|out|std_logic_vector ( 07 downto 00 )|Counter of error detected on the RX link|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#86">RX_ERROR_OVF</linty-anchor>|out|std_logic|Overflow flag of the RX_ERROR_CNT|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#87">LOSS_SIGNAL</linty-anchor>|out|std_logic|Set when no signal is received on RX link|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#88">FAR_END_CAPA</linty-anchor>|out|std_logic_vector ( 07 downto 00 )|Capabilities field (INT3 flags)|
|<linty-anchor href="//src/module_phy_plus_lane/phy_plus_lane.vhd#89">RX_POLARITY</linty-anchor>|out|std_logic|Set when the receiver polarity is inverted|


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